[GlobalISel] Combine and (lshr x, cst), mask -> ubfx x, cst, width

[paquette]

Summary

Only do this post-legalization for now

This is generic now.

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

3931

The amounts could be a different type from the value, so I guess I'll need to fix that in the instruction definition

3956

getScalarSizeInBits

[paquette]

Rebase + move to AArch64-only to match the G_SBFX combine. Maybe this can be cannibalized into something more generic.

[jroelofs]

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

289 ↗

(On Diff #345197)

What is the range of AndImm at this point? I'm worried that we'll have UB if the addition overflows.

[paquette]

• Fix UB by doing all the computations on unsigned ints (which is what SDAG does anyway)
• Simplify the logic a little bit more
• Add boundary testcases which use signed + unsigned max integer values

(Maybe there should be a m_UICst(...) matcher or something...?)

[arsenm]

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

282–285 ↗

(On Diff #346771)

This is the only target specific thing here which can be replaced with a legality check on UBFX

308 ↗

(On Diff #346771)

buildUbfx?

llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir

4

Why does this need asserts?

[paquette]

llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir

4

The only-enable-rule stuff only works with asserts.

[paquette]

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

282–285 ↗

(On Diff #346771)

The annoying part (for AArch64) is that the legality checks don't work with custom legalization.

I'm not sure what the best way to handle custom actions is.

[arsenm]

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

282–285 ↗

(On Diff #346771)

That's what we usually end up adding TLI hooks for, although they're terrible

[paquette]

Make this a generic combine + add a target hook to define when it should be enabled.

[jroelofs]

LGTM

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

4002

Depending on subtarget-specific latencies, this may be worthwhile even when the shift has more than one use if lat(ubfx) < lat(and) + lat(lshr).

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

public:
   void applyFunnelShiftToRotate(MachineInstr &MI);
   bool matchRotateOutOfRange(MachineInstr &MI);
   void applyRotateOutOfRange(MachineInstr &MI);
 
   /// \returns true if a G_ICMP instruction \p MI can be replaced with a true
   /// or false constant based off of KnownBits information.
   bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo);
 
+  /// Match: and (lshr x, cst), mask -> ubfx x, cst, width
+  bool matchBitfieldExtractFromAnd(
+      MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo);
+
   /// Try to transform \p MI by using all of the above
   /// combine functions. Returns true if changed.
   bool tryCombine(MachineInstr &MI);
 
 private:
   // Memcpy family optimization helpers.
   bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
                       unsigned KnownLen, Align DstAlign, Align SrcAlign,

llvm/include/llvm/CodeGen/TargetLowering.h

#include "llvm/IR/ConstrainedOps.def"
   virtual bool useStackGuardXorFP() const { return false; }
 
   /// If the target has a standard stack protection check function that
   /// performs validation and error handling, returns the function. Otherwise,
   /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
   /// Should be used only when getIRStackGuard returns nullptr.
   virtual Function *getSSPStackGuardCheck(const Module &M) const;
 
+  /// \returns true if a constant G_UBFX is legal on the target.
+  virtual bool isConstantUnsignedBitfieldExtactLegal(unsigned Opc, LLT Ty1,
+                                                     LLT Ty2) const {
+    return false;
+  }
+
 protected:
   Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
                                             bool UseTLS) const;
 
 public:
   /// Returns the target-specific address of the unsafe stack pointer.
   virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
 

llvm/include/llvm/Target/GlobalISel/Combine.td

 >;
 
 def icmp_to_true_false_known_bits : GICombineRule<
   (defs root:$d, int64_matchinfo:$matchinfo),
   (match (wip_match_opcode G_ICMP):$d,
          [{ return Helper.matchICmpToTrueFalseKnownBits(*${d}, ${matchinfo}); }]),
   (apply [{ Helper.replaceInstWithConstant(*${d}, ${matchinfo}); }])>;
 
+def bitfield_extract_from_and : GICombineRule<
+  (defs root:$root, build_fn_matchinfo:$info),
+  (match (wip_match_opcode G_AND):$root,
+    [{ return Helper.matchBitfieldExtractFromAnd(*${root}, ${info}); }]),
+  (apply [{ return Helper.applyBuildFn(*${root}, ${info}); }])>;
+
 def funnel_shift_combines : GICombineGroup<[funnel_shift_to_rotate]>;
 
 // FIXME: These should use the custom predicate feature once it lands.
 def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
                                      undef_to_negative_one,
                                      binop_left_undef_to_zero,
                                      propagate_undef_any_op,
                                      propagate_undef_all_ops,
def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
     shl_ashr_to_sext_inreg, sext_inreg_of_load,
     width_reduction_combines, select_combines,
     known_bits_simplifications, ext_ext_fold,
     not_cmp_fold, opt_brcond_by_inverting_cond,
     unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc,
     unmerge_zext_to_zext, trunc_ext_fold, trunc_shl,
     const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
     shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
-    div_rem_to_divrem, funnel_shift_combines]>;
+    div_rem_to_divrem, funnel_shift_combines, bitfield_extract_from_and]>;
 
 // A combine group used to for prelegalizer combiners at -O0. The combines in
 // this group have been selected based on experiments to balance code size and
 // compile time performance.
 def optnone_combines : GICombineGroup<[trivial_combines,
     ptr_add_immed_chain, combines_for_extload,
     not_cmp_fold, opt_brcond_by_inverting_cond]>;

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

assert(MI.getOpcode() == TargetOpcode::G_ROTL ||
          MI.getOpcode() == TargetOpcode::G_ROTR);
   unsigned Bitsize =
       MRI.getType(MI.getOperand(0).getReg()).getScalarSizeInBits();
   Builder.setInstrAndDebugLoc(MI);
   Register Amt = MI.getOperand(2).getReg();
   LLT AmtTy = MRI.getType(Amt);
   auto Bits = Builder.buildConstant(AmtTy, Bitsize);
   Amt = Builder.buildURem(AmtTy, MI.getOperand(2).getReg(), Bits).getReg(0);
   Observer.changingInstr(MI);
   MI.getOperand(2).setReg(Amt);
   Observer.changedInstr(MI);
 }
 
 bool CombinerHelper::matchICmpToTrueFalseKnownBits(MachineInstr &MI,
                                                    int64_t &MatchInfo) {
   assert(MI.getOpcode() == TargetOpcode::G_ICMP);
   auto Pred = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
   auto KnownLHS = KB->getKnownBits(MI.getOperand(2).getReg());
   auto KnownRHS = KB->getKnownBits(MI.getOperand(3).getReg());
   Optional<bool> KnownVal;
   switch (Pred) {
   default:
     llvm_unreachable("Unexpected G_ICMP predicate?");
   case CmpInst::ICMP_EQ:
     KnownVal = KnownBits::eq(KnownLHS, KnownRHS);
     break;
   case CmpInst::ICMP_NE:
     KnownVal = KnownBits::ne(KnownLHS, KnownRHS);
     break;
   case CmpInst::ICMP_SGE:
     KnownVal = KnownBits::sge(KnownLHS, KnownRHS);
     break;
   case CmpInst::ICMP_SGT:
     KnownVal = KnownBits::sgt(KnownLHS, KnownRHS);
     break;
   case CmpInst::ICMP_SLE:
     KnownVal = KnownBits::sle(KnownLHS, KnownRHS);
     break;
   case CmpInst::ICMP_SLT:
     KnownVal = KnownBits::slt(KnownLHS, KnownRHS);
     break;
   case CmpInst::ICMP_UGE:
MatchInfo =
           ? getICmpTrueVal(getTargetLowering(),
                            /*IsVector = */
                            MRI.getType(MI.getOperand(0).getReg()).isVector(),
                            /* IsFP = */ false)
           : 0;
   return true;
 }
 
+bool CombinerHelper::matchBitfieldExtractFromAnd(
+    MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo) {
+  assert(MI.getOpcode() == TargetOpcode::G_AND);
+  Register Dst = MI.getOperand(0).getReg();
+  LLT Ty = MRI.getType(Dst);
+  if (!getTargetLowering().isConstantUnsignedBitfieldExtactLegal(
+          TargetOpcode::G_UBFX, Ty, Ty))
+    return false;
+
+  int64_t AndImm, LSBImm;
+  Register ShiftSrc;
+  const unsigned Size = Ty.getScalarSizeInBits();
+  if (!mi_match(MI.getOperand(0).getReg(), MRI,
+                m_GAnd(m_OneNonDBGUse(m_GLShr(m_Reg(ShiftSrc), m_ICst(LSBImm))),
+                       m_ICst(AndImm))))
+    return false;
+
+  // The mask is a mask of the low bits iff imm & (imm+1) == 0.
+  auto MaybeMask = static_cast<uint64_t>(AndImm);
+  if (MaybeMask & (MaybeMask + 1))
+    return false;
+
+  // LSB must fit within the register.
+  if (static_cast<uint64_t>(LSBImm) >= Size)
+    return false;
+
+  uint64_t Width = APInt(Size, AndImm).countTrailingOnes();
+  MatchInfo = [=](MachineIRBuilder &B) {
+    auto WidthCst = B.buildConstant(Ty, Width);
+    auto LSBCst = B.buildConstant(Ty, LSBImm);
+    B.buildInstr(TargetOpcode::G_UBFX, {Dst}, {ShiftSrc, LSBCst, WidthCst});
+  };
+  return true;
+}
+
 bool CombinerHelper::tryCombine(MachineInstr &MI) {
   if (tryCombineCopy(MI))
     return true;
   if (tryCombineExtendingLoads(MI))
     return true;
   if (tryCombineIndexedLoadStore(MI))
     return true;
   return false;
 }

llvm/lib/Target/AArch64/AArch64Combine.td

 def build_vector_lowering : GICombineGroup<[build_vector_to_dup]>;
 
 def bitfield_extract_from_sext_inreg : GICombineRule<
   (defs root:$root, build_fn_matchinfo:$info),
   (match (wip_match_opcode G_SEXT_INREG):$root,
     [{ return matchBitfieldExtractFromSExtInReg(*${root}, MRI, ${info}); }]),
   (apply [{ return Helper.applyBuildFn(*${root}, ${info}); }])>;
 
-def form_bitfield_extract : GICombineGroup<[bitfield_extract_from_sext_inreg]>;
+def form_bitfield_extract : GICombineGroup<[bitfield_extract_from_sext_inreg,
+                                            bitfield_extract_from_and]>;
 
 def lower_vector_fcmp : GICombineRule<
   (defs root:$root),
   (match (wip_match_opcode G_FCMP):$root,
     [{ return lowerVectorFCMP(*${root}, MRI, B); }]),
   (apply [{}])>;
 
 def form_truncstore_matchdata : GIDefMatchData<"Register">;

llvm/lib/Target/AArch64/AArch64ISelLowering.h

private:
   //  1. Packed and unpacked types have different bit lengths, meaning BITCAST
   //     is not universally useable.
   //  2. Most unpacked integer types are not legal and thus integer extends
   //     cannot be used to convert between unpacked and packed types.
   // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used
   // to transition between unpacked and packed types of the same element type,
   // with BITCAST used otherwise.
   SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
+
+  bool isConstantUnsignedBitfieldExtactLegal(unsigned Opc, LLT Ty1,
+                                             LLT Ty2) const override;
 };
 
 namespace AArch64 {
 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
                          const TargetLibraryInfo *libInfo);
 } // end namespace AArch64
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

case AArch64ISD::VSHL: {
     // used - simplify to just Val.
     return TLO.CombineTo(Op, ShiftR->getOperand(0));
   }
   }
 
   return TargetLowering::SimplifyDemandedBitsForTargetNode(
       Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
 }
+
+bool AArch64TargetLowering::isConstantUnsignedBitfieldExtactLegal(
+    unsigned Opc, LLT Ty1, LLT Ty2) const {
+  return Ty1 == Ty2 && (Ty1 == LLT::scalar(32) || Ty1 == LLT::scalar(64));
+}

llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner --aarch64postlegalizercombinerhelper-only-enable-rule="bitfield_extract_from_and" -verify-machineinstrs %s -o - | FileCheck %s
+# REQUIRES: asserts
+
+# Check that we can combine
+#
+# and (lshr x, cst), mask -> ubfx x, cst, width
+
+...
+---
+name:            ubfx_s32
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $w0
+
+    ; LSB = 5
+    ; Width = LSB + trailing_ones(255) - 1 =
+    ;         5 + 8 - 1 = 12
+
+    ; CHECK-LABEL: name: ubfx_s32
+    ; CHECK: liveins: $w0
+    ; CHECK: %x:_(s32) = COPY $w0
+    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 5
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: %and:_(s32) = G_UBFX %x, %lsb(s32), [[C]]
+    ; CHECK: $w0 = COPY %and(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %lsb:_(s32) = G_CONSTANT i32 5
+    %mask:_(s32) = G_CONSTANT i32 255
+    %shift:_(s32) = G_LSHR %x, %lsb
+    %and:_(s32) = G_AND %shift, %mask
+    $w0 = COPY %and
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            ubfx_s64
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $x0
+
+    ; LSB = 5
+    ; Width = LSB + trailing_ones(1) - 1 =
+    ;         5 + 1 - 1 = 5
+
+    ; CHECK-LABEL: name: ubfx_s64
+    ; CHECK: liveins: $x0
+    ; CHECK: %x:_(s64) = COPY $x0
+    ; CHECK: %lsb:_(s64) = G_CONSTANT i64 5
+    ; CHECK: %mask:_(s64) = G_CONSTANT i64 1
+    ; CHECK: %and:_(s64) = G_UBFX %x, %lsb(s64), %mask
+    ; CHECK: $x0 = COPY %and(s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %x:_(s64) = COPY $x0
+    %lsb:_(s64) = G_CONSTANT i64 5
+    %mask:_(s64) = G_CONSTANT i64 1
+    %shift:_(s64) = G_LSHR %x, %lsb
+    %and:_(s64) = G_AND %shift, %mask
+    $x0 = COPY %and
+    RET_ReallyLR implicit $x0
+
+...
+---
+name:            dont_combine_no_and_cst
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+
+    ; UBFX needs to be selected to UBFMWri/UBFMXri, so we need constants.
+
+    ; CHECK-LABEL: name: dont_combine_no_and_cst
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK: %x:_(s32) = COPY $w0
+    ; CHECK: %y:_(s32) = COPY $w1
+    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 5
+    ; CHECK: %shift:_(s32) = G_LSHR %x, %lsb(s32)
+    ; CHECK: %and:_(s32) = G_AND %shift, %y
+    ; CHECK: $w0 = COPY %and(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %y:_(s32) = COPY $w1
+    %lsb:_(s32) = G_CONSTANT i32 5
+    %shift:_(s32) = G_LSHR %x, %lsb
+    %and:_(s32) = G_AND %shift, %y
+    $w0 = COPY %and
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            dont_combine_and_cst_not_mask
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $w0
+    ; CHECK-LABEL: name: dont_combine_and_cst_not_mask
+    ; CHECK: liveins: $w0
+    ; CHECK: %x:_(s32) = COPY $w0
+    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 5
+    ; CHECK: %not_a_mask:_(s32) = G_CONSTANT i32 2
+    ; CHECK: %shift:_(s32) = G_LSHR %x, %lsb(s32)
+    ; CHECK: %and:_(s32) = G_AND %shift, %not_a_mask
+    ; CHECK: $w0 = COPY %and(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %lsb:_(s32) = G_CONSTANT i32 5
+    %not_a_mask:_(s32) = G_CONSTANT i32 2
+    %shift:_(s32) = G_LSHR %x, %lsb
+    %and:_(s32) = G_AND %shift, %not_a_mask
+    $w0 = COPY %and
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            dont_combine_shift_more_than_one_use
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: dont_combine_shift_more_than_one_use
+    ; CHECK: liveins: $x0
+    ; CHECK: %x:_(s64) = COPY $x0
+    ; CHECK: %lsb:_(s64) = G_CONSTANT i64 5
+    ; CHECK: %mask:_(s64) = G_CONSTANT i64 1
+    ; CHECK: %shift:_(s64) = G_LSHR %x, %lsb(s64)
+    ; CHECK: %and:_(s64) = G_AND %shift, %mask
+    ; CHECK: %sub:_(s64) = G_SUB %and, %shift
+    ; CHECK: $x0 = COPY %sub(s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %x:_(s64) = COPY $x0
+    %lsb:_(s64) = G_CONSTANT i64 5
+    %mask:_(s64) = G_CONSTANT i64 1
+    %shift:_(s64) = G_LSHR %x, %lsb
+    %and:_(s64) = G_AND %shift, %mask
+    %sub:_(s64) = G_SUB %and, %shift
+    $x0 = COPY %sub
+    RET_ReallyLR implicit $x0
+
+...
+---
+name:            dont_combine_negative_lsb
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $w0
+
+    ; LSB must be in [0, reg_size)
+
+    ; CHECK-LABEL: name: dont_combine_negative_lsb
+    ; CHECK: liveins: $w0
+    ; CHECK: %x:_(s32) = COPY $w0
+    ; CHECK: %negative:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: %mask:_(s32) = G_CONSTANT i32 255
+    ; CHECK: %shift:_(s32) = G_LSHR %x, %negative(s32)
+    ; CHECK: %and:_(s32) = G_AND %shift, %mask
+    ; CHECK: $w0 = COPY %and(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %negative:_(s32) = G_CONSTANT i32 -1
+    %mask:_(s32) = G_CONSTANT i32 255
+    %shift:_(s32) = G_LSHR %x, %negative
+    %and:_(s32) = G_AND %shift, %mask
+    $w0 = COPY %and
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            dont_combine_lsb_too_large
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $w0
+
+    ; LSB must be in [0, reg_size)
+
+    ; CHECK-LABEL: name: dont_combine_lsb_too_large
+    ; CHECK: liveins: $w0
+    ; CHECK: %x:_(s32) = COPY $w0
+    ; CHECK: %too_large:_(s32) = G_CONSTANT i32 32
+    ; CHECK: %mask:_(s32) = G_CONSTANT i32 255
+    ; CHECK: %shift:_(s32) = G_LSHR %x, %too_large(s32)
+    ; CHECK: %and:_(s32) = G_AND %shift, %mask
+    ; CHECK: $w0 = COPY %and(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %x:_(s32) = COPY $w0
+    %too_large:_(s32) = G_CONSTANT i32 32
+    %mask:_(s32) = G_CONSTANT i32 255
+    %shift:_(s32) = G_LSHR %x, %too_large
+    %and:_(s32) = G_AND %shift, %mask
+    $w0 = COPY %and
+    RET_ReallyLR implicit $w0
+
+...
+---
+name:            dont_combine_vector
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: dont_combine_vector
+    ; CHECK: liveins: $d0
+    ; CHECK: %x:_(<2 x s32>) = COPY $d0
+    ; CHECK: %lsb_cst:_(s32) = G_CONSTANT i32 5
+    ; CHECK: %lsb:_(<2 x s32>) = G_BUILD_VECTOR %lsb_cst(s32), %lsb_cst(s32)
+    ; CHECK: %mask_cst:_(s32) = G_CONSTANT i32 255
+    ; CHECK: %mask:_(<2 x s32>) = G_BUILD_VECTOR %mask_cst(s32), %mask_cst(s32)
+    ; CHECK: %shift:_(<2 x s32>) = G_LSHR %x, %lsb(<2 x s32>)
+    ; CHECK: %and:_(<2 x s32>) = G_AND %shift, %mask
+    ; CHECK: $d0 = COPY %and(<2 x s32>)
+    ; CHECK: RET_ReallyLR implicit $d0
+    %x:_(<2 x s32>) = COPY $d0
+    %lsb_cst:_(s32) = G_CONSTANT i32 5
+    %lsb:_(<2 x s32>) = G_BUILD_VECTOR %lsb_cst, %lsb_cst
+    %mask_cst:_(s32) = G_CONSTANT i32 255
+    %mask:_(<2 x s32>) = G_BUILD_VECTOR %mask_cst, %mask_cst
+    %shift:_(<2 x s32>) = G_LSHR %x, %lsb
+    %and:_(<2 x s32>) = G_AND %shift, %mask
+    $d0 = COPY %and
+    RET_ReallyLR implicit $d0
+
+...
+---
+name:            max_signed_int_mask
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $x0
+    ; mask = 0111 1111 1111 ... 1111
+    ; mask + 1 = 1000 0000 0000 ... 0000
+    ; CHECK-LABEL: name: max_signed_int_mask
+    ; CHECK: liveins: $x0
+    ; CHECK: %x:_(s64) = COPY $x0
+    ; CHECK: %lsb:_(s64) = G_CONSTANT i64 0
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+    ; CHECK: %and:_(s64) = G_UBFX %x, %lsb(s64), [[C]]
+    ; CHECK: $x0 = COPY %and(s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %x:_(s64) = COPY $x0
+    %lsb:_(s64) = G_CONSTANT i64 0
+    %mask:_(s64) = G_CONSTANT i64 9223372036854775807
+    %shift:_(s64) = G_LSHR %x, %lsb
+    %and:_(s64) = G_AND %shift, %mask
+    $x0 = COPY %and
+    RET_ReallyLR implicit $x0
+
+...
+---
+name:            max_unsigned_int_mask
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $x0
+    ; mask = 1111 1111 1111 ... 1111
+    ; mask + 1 = 0000 0000 0000 ... 000
+    ; CHECK-LABEL: name: max_unsigned_int_mask
+    ; CHECK: liveins: $x0
+    ; CHECK: %x:_(s64) = COPY $x0
+    ; CHECK: %lsb:_(s64) = G_CONSTANT i64 5
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+    ; CHECK: %and:_(s64) = G_UBFX %x, %lsb(s64), [[C]]
+    ; CHECK: $x0 = COPY %and(s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %x:_(s64) = COPY $x0
+    %lsb:_(s64) = G_CONSTANT i64 5
+    %mask:_(s64) = G_CONSTANT i64 18446744073709551615
+    %shift:_(s64) = G_LSHR %x, %lsb
+    %and:_(s64) = G_AND %shift, %mask
+    $x0 = COPY %and
+    RET_ReallyLR implicit $x0