diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -82,16 +82,16 @@ Sched<[WriteFST64, ReadStoreData, ReadFMemBase]>; def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">, - Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>; + Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>; def : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">; def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">, - Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>; + Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>; def : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">; def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">, - Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>; + Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>; def : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">; def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">, - Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>; + Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>; def : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">; def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -117,16 +117,16 @@ Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>; def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">, - Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>; + Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; def : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">; def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">, - Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>; + Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; def : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">; def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">, - Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>; + Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; def : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">; def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">, - Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>; + Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; def : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">; def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td @@ -83,16 +83,16 @@ Sched<[WriteFST16, ReadStoreData, ReadFMemBase]>; def FMADD_H : FPFMAH_rrr_frm<OPC_MADD, "fmadd.h">, - Sched<[WriteFMulAdd16, ReadFMulAdd16, ReadFMulAdd16, ReadFMulAdd16]>; + Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>; def : FPFMAHDynFrmAlias<FMADD_H, "fmadd.h">; def FMSUB_H : FPFMAH_rrr_frm<OPC_MSUB, "fmsub.h">, - Sched<[WriteFMulSub16, ReadFMulSub16, ReadFMulSub16, ReadFMulSub16]>; + Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>; def : FPFMAHDynFrmAlias<FMSUB_H, "fmsub.h">; def FNMSUB_H : FPFMAH_rrr_frm<OPC_NMSUB, "fnmsub.h">, - Sched<[WriteFMulSub16, ReadFMulSub16, ReadFMulSub16, ReadFMulSub16]>; + Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>; def : FPFMAHDynFrmAlias<FNMSUB_H, "fnmsub.h">; def FNMADD_H : FPFMAH_rrr_frm<OPC_NMADD, "fnmadd.h">, - Sched<[WriteFMulAdd16, ReadFMulAdd16, ReadFMulAdd16, ReadFMulAdd16]>; + Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>; def : FPFMAHDynFrmAlias<FNMADD_H, "fnmadd.h">; def FADD_H : FPALUH_rr_frm<0b0000010, "fadd.h">, diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -145,14 +145,12 @@ // FP multiplication let Latency = 5 in { def : WriteRes<WriteFMul32, [RocketUnitFPALU]>; -def : WriteRes<WriteFMulAdd32, [RocketUnitFPALU]>; -def : WriteRes<WriteFMulSub32, [RocketUnitFPALU]>; +def : WriteRes<WriteFMA32, [RocketUnitFPALU]>; } let Latency = 7 in { def : WriteRes<WriteFMul64, [RocketUnitFPALU]>; -def : WriteRes<WriteFMulAdd64, [RocketUnitFPALU]>; -def : WriteRes<WriteFMulSub64, [RocketUnitFPALU]>; +def : WriteRes<WriteFMA64, [RocketUnitFPALU]>; } // FP division @@ -203,11 +201,9 @@ def : ReadAdvance<ReadFALU32, 0>; def : ReadAdvance<ReadFALU64, 0>; def : ReadAdvance<ReadFMul32, 0>; -def : ReadAdvance<ReadFMulAdd32, 0>; -def : ReadAdvance<ReadFMulSub32, 0>; +def : ReadAdvance<ReadFMA32, 0>; def : ReadAdvance<ReadFMul64, 0>; -def : ReadAdvance<ReadFMulAdd64, 0>; -def : ReadAdvance<ReadFMulSub64, 0>; +def : ReadAdvance<ReadFMA64, 0>; def : ReadAdvance<ReadFDiv32, 0>; def : ReadAdvance<ReadFDiv64, 0>; def : ReadAdvance<ReadFSqrt32, 0>; @@ -250,9 +246,8 @@ def : WriteRes<WriteFDiv16, []>; def : WriteRes<WriteFCmp16, []>; def : WriteRes<WriteFLD16, []>; -def : WriteRes<WriteFMulAdd16, []>; +def : WriteRes<WriteFMA16, []>; def : WriteRes<WriteFMinMax16, []>; -def : WriteRes<WriteFMulSub16, []>; def : WriteRes<WriteFMul16, []>; def : WriteRes<WriteFMovI16ToF16, []>; def : WriteRes<WriteFMovF16ToI16, []>; @@ -272,9 +267,8 @@ def : ReadAdvance<ReadFCvtF16ToI32, 0>; def : ReadAdvance<ReadFDiv16, 0>; def : ReadAdvance<ReadFCmp16, 0>; -def : ReadAdvance<ReadFMulAdd16, 0>; +def : ReadAdvance<ReadFMA16, 0>; def : ReadAdvance<ReadFMinMax16, 0>; -def : ReadAdvance<ReadFMulSub16, 0>; def : ReadAdvance<ReadFMul16, 0>; def : ReadAdvance<ReadFMovI16ToF16, 0>; def : ReadAdvance<ReadFMovF16ToI16, 0>; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -103,8 +103,7 @@ let Latency = 5 in { def : WriteRes<WriteFALU32, [SiFive7PipeB]>; def : WriteRes<WriteFMul32, [SiFive7PipeB]>; -def : WriteRes<WriteFMulAdd32, [SiFive7PipeB]>; -def : WriteRes<WriteFMulSub32, [SiFive7PipeB]>; +def : WriteRes<WriteFMA32, [SiFive7PipeB]>; } let Latency = 3 in { def : WriteRes<WriteFSGNJ32, [SiFive7PipeB]>; @@ -120,8 +119,7 @@ let Latency = 7 in { def : WriteRes<WriteFALU64, [SiFive7PipeB]>; def : WriteRes<WriteFMul64, [SiFive7PipeB]>; -def : WriteRes<WriteFMulAdd64, [SiFive7PipeB]>; -def : WriteRes<WriteFMulSub64, [SiFive7PipeB]>; +def : WriteRes<WriteFMA64, [SiFive7PipeB]>; } let Latency = 3 in { def : WriteRes<WriteFSGNJ64, [SiFive7PipeB]>; @@ -191,11 +189,9 @@ def : ReadAdvance<ReadFALU32, 0>; def : ReadAdvance<ReadFALU64, 0>; def : ReadAdvance<ReadFMul32, 0>; -def : ReadAdvance<ReadFMulAdd32, 0>; -def : ReadAdvance<ReadFMulSub32, 0>; +def : ReadAdvance<ReadFMA32, 0>; def : ReadAdvance<ReadFMul64, 0>; -def : ReadAdvance<ReadFMulAdd64, 0>; -def : ReadAdvance<ReadFMulSub64, 0>; +def : ReadAdvance<ReadFMA64, 0>; def : ReadAdvance<ReadFDiv32, 0>; def : ReadAdvance<ReadFDiv64, 0>; def : ReadAdvance<ReadFSqrt32, 0>; @@ -238,9 +234,8 @@ def : WriteRes<WriteFDiv16, []>; def : WriteRes<WriteFCmp16, []>; def : WriteRes<WriteFLD16, []>; -def : WriteRes<WriteFMulAdd16, []>; +def : WriteRes<WriteFMA16, []>; def : WriteRes<WriteFMinMax16, []>; -def : WriteRes<WriteFMulSub16, []>; def : WriteRes<WriteFMul16, []>; def : WriteRes<WriteFMovI16ToF16, []>; def : WriteRes<WriteFMovF16ToI16, []>; @@ -260,9 +255,8 @@ def : ReadAdvance<ReadFCvtF16ToI32, 0>; def : ReadAdvance<ReadFDiv16, 0>; def : ReadAdvance<ReadFCmp16, 0>; -def : ReadAdvance<ReadFMulAdd16, 0>; +def : ReadAdvance<ReadFMA16, 0>; def : ReadAdvance<ReadFMinMax16, 0>; -def : ReadAdvance<ReadFMulSub16, 0>; def : ReadAdvance<ReadFMul16, 0>; def : ReadAdvance<ReadFMovI16ToF16, 0>; def : ReadAdvance<ReadFMovF16ToI16, 0>; diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td --- a/llvm/lib/Target/RISCV/RISCVSchedule.td +++ b/llvm/lib/Target/RISCV/RISCVSchedule.td @@ -42,14 +42,11 @@ def WriteFALU32 : SchedWrite; // FP 32-bit computation def WriteFALU64 : SchedWrite; // FP 64-bit computation def WriteFMul16 : SchedWrite; // 16-bit floating point multiply -def WriteFMulAdd16 : SchedWrite; // 16-bit floating point multiply add -def WriteFMulSub16 : SchedWrite; // 16-bit floating point multiply sub +def WriteFMA16 : SchedWrite; // 16-bit floating point fused multiply-add def WriteFMul32 : SchedWrite; // 32-bit floating point multiply -def WriteFMulAdd32 : SchedWrite; // 32-bit floating point multiply add -def WriteFMulSub32 : SchedWrite; // 32-bit floating point multiply sub +def WriteFMA32 : SchedWrite; // 32-bit floating point fused multiply-add def WriteFMul64 : SchedWrite; // 64-bit floating point multiply -def WriteFMulAdd64 : SchedWrite; // 64-bit floating point multiply add -def WriteFMulSub64 : SchedWrite; // 64-bit floating point multiply sub +def WriteFMA64 : SchedWrite; // 64-bit floating point fused multiply-add def WriteFDiv16 : SchedWrite; // 16-bit floating point divide def WriteFDiv32 : SchedWrite; // 32-bit floating point divide def WriteFDiv64 : SchedWrite; // 64-bit floating point divide @@ -155,14 +152,11 @@ def ReadFALU32 : SchedRead; // FP 32-bit computation def ReadFALU64 : SchedRead; // FP 64-bit computation def ReadFMul16 : SchedRead; // 16-bit floating point multiply -def ReadFMulAdd16 : SchedRead; // 16-bit floating point multiply add -def ReadFMulSub16 : SchedRead; // 16-bit floating point multiply sub +def ReadFMA16 : SchedRead; // 16-bit floating point fused multiply-add def ReadFMul32 : SchedRead; // 32-bit floating point multiply -def ReadFMulAdd32 : SchedRead; // 32-bit floating point multiply add -def ReadFMulSub32 : SchedRead; // 32-bit floating point multiply sub +def ReadFMA32 : SchedRead; // 32-bit floating point fused multiply-add def ReadFMul64 : SchedRead; // 64-bit floating point multiply -def ReadFMulAdd64 : SchedRead; // 64-bit floating point multiply add -def ReadFMulSub64 : SchedRead; // 64-bit floating point multiply sub +def ReadFMA64 : SchedRead; // 64-bit floating point fused multiply-add def ReadFDiv16 : SchedRead; // 16-bit floating point divide def ReadFDiv32 : SchedRead; // 32-bit floating point divide def ReadFDiv64 : SchedRead; // 64-bit floating point divide