diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1216,6 +1216,18 @@ return Imm.isExactlyValue(+0.0); }]>; +def fpimm_half : FPImmLeaf; + +def fpimm_one : FPImmLeaf; + +def fpimm_two : FPImmLeaf; + def gi_fpimm16 : GICustomOperandRenderer<"renderFPImm16">, GISDNodeXFormEquiv; def gi_fpimm32 : GICustomOperandRenderer<"renderFPImm32">, diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -405,14 +405,34 @@ defm FRECPE_ZZ : sve_fp_2op_u_zd<0b110, "frecpe", int_aarch64_sve_frecpe_x>; defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte", int_aarch64_sve_frsqrte_x>; - defm FADD_ZPmI : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>; - defm FSUB_ZPmI : sve_fp_2op_i_p_zds<0b001, "fsub", sve_fpimm_half_one>; - defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>; - defm FSUBR_ZPmI : sve_fp_2op_i_p_zds<0b011, "fsubr", sve_fpimm_half_one>; - defm FMAXNM_ZPmI : sve_fp_2op_i_p_zds<0b100, "fmaxnm", sve_fpimm_zero_one>; - defm FMINNM_ZPmI : sve_fp_2op_i_p_zds<0b101, "fminnm", sve_fpimm_zero_one>; - defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>; - defm FMIN_ZPmI : sve_fp_2op_i_p_zds<0b111, "fmin", sve_fpimm_zero_one>; + defm FADD_ZPmI : sve_fp_2op_i_p_zds<0b000, "fadd", "FADD_ZPZI", sve_fpimm_half_one, fpimm_half, fpimm_one, int_aarch64_sve_fadd>; + defm FSUB_ZPmI : sve_fp_2op_i_p_zds<0b001, "fsub", "FSUB_ZPZI", sve_fpimm_half_one, fpimm_half, fpimm_one, int_aarch64_sve_fsub>; + defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", "FMUL_ZPZI", sve_fpimm_half_two, fpimm_half, fpimm_two, int_aarch64_sve_fmul>; + defm FSUBR_ZPmI : sve_fp_2op_i_p_zds<0b011, "fsubr", "FSUBR_ZPZI", sve_fpimm_half_one, fpimm_half, fpimm_one, int_aarch64_sve_fsubr>; + defm FMAXNM_ZPmI : sve_fp_2op_i_p_zds<0b100, "fmaxnm", "FMAXNM_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fmaxnm>; + defm FMINNM_ZPmI : sve_fp_2op_i_p_zds<0b101, "fminnm", "FMINNM_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fminnm>; + defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", "FMAX_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fmax>; + defm FMIN_ZPmI : sve_fp_2op_i_p_zds<0b111, "fmin", "FMIN_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fmin>; + + defm FADD_ZPZI : sve_fp_2op_i_p_zds_hfd; + defm FSUB_ZPZI : sve_fp_2op_i_p_zds_hfd; + defm FMUL_ZPZI : sve_fp_2op_i_p_zds_hfd; + defm FSUBR_ZPZI : sve_fp_2op_i_p_zds_hfd; + defm FMAXNM_ZPZI : sve_fp_2op_i_p_zds_hfd; + defm FMINNM_ZPZI : sve_fp_2op_i_p_zds_hfd; + defm FMAX_ZPZI : sve_fp_2op_i_p_zds_hfd; + defm FMIN_ZPZI : sve_fp_2op_i_p_zds_hfd; + + let Predicates = [HasSVE, UseExperimentalZeroingPseudos] in { + defm FADD_ZPZI : sve_fp_2op_i_p_zds_zeroing_hfd; + defm FSUB_ZPZI : sve_fp_2op_i_p_zds_zeroing_hfd; + defm FMUL_ZPZI : sve_fp_2op_i_p_zds_zeroing_hfd; + defm FSUBR_ZPZI : sve_fp_2op_i_p_zds_zeroing_hfd; + defm FMAXNM_ZPZI : sve_fp_2op_i_p_zds_zeroing_hfd; + defm FMINNM_ZPZI : sve_fp_2op_i_p_zds_zeroing_hfd; + defm FMAX_ZPZI : sve_fp_2op_i_p_zds_zeroing_hfd; + defm FMIN_ZPZI : sve_fp_2op_i_p_zds_zeroing_hfd; + } defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd", "FADD_ZPZZ", int_aarch64_sve_fadd, DestructiveBinaryComm>; defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub", "FSUB_ZPZZ", int_aarch64_sve_fsub, DestructiveBinaryCommWithRev, "FSUBR_ZPmZ">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -490,6 +490,21 @@ : Pat<(vt (op (pt (SVEAllActive)), vt:$Rn, (vt (AArch64dup (it (cast i32:$imm)))))), (inst $Rn, i32:$imm)>; +class SVE_2_Op_Fp_Imm_Pat +: Pat<(vt (op (pt PPR_3b:$Pg), (vt ZPR:$Zs1), (vt (AArch64dup (it immL))))), + (inst $Pg, $Zs1, imm)>; + +class SVE_2_Op_Fp_Imm_Pat_Zero +: Pat<(vt (op pt:$Pg, (vselect pt:$Pg, vt:$Zs1, (SVEDup0)), + (vt (AArch64dup (it immL))))), + (inst $Pg, $Zs1, imm)>; + // // Pseudo -> Instruction mappings // @@ -1745,10 +1760,19 @@ let ElementSize = zprty.ElementSize; } -multiclass sve_fp_2op_i_p_zds opc, string asm, Operand imm_ty> { - def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>; - def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>; - def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>; +multiclass sve_fp_2op_i_p_zds opc, string asm, string Ps, Operand imm_ty, FPImmLeaf A, FPImmLeaf B, SDPatternOperator op> { + let DestructiveInstType = DestructiveBinaryImm in { + def _H : SVEPseudo2Instr, sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>; + def _S : SVEPseudo2Instr, sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>; + def _D : SVEPseudo2Instr, sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>; + } + + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_H")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_H")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_S")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_S")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_D")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_D")>; } class sve_fp_2op_p_zds sz, bits<4> opc, string asm, @@ -1846,6 +1870,40 @@ (!cast(NAME # _D) ZPR64:$Zn, ZPR64:$Zm, imm32_0_7:$imm)>; } +multiclass sve_fp_2op_i_p_zds_hfd { + def _UNDEF_H : PredTwoOpImmPseudo; + def _UNDEF_S : PredTwoOpImmPseudo; + def _UNDEF_D : PredTwoOpImmPseudo; + + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_H")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_H")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_H")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_H")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_H")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_H")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_S")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_S")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_S")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_S")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_D")>; + def : SVE_2_Op_Fp_Imm_Pat(NAME # "_UNDEF_D")>; +} + +multiclass sve_fp_2op_i_p_zds_zeroing_hfd { + def _ZERO_H : PredTwoOpImmPseudo; + def _ZERO_S : PredTwoOpImmPseudo; + def _ZERO_D : PredTwoOpImmPseudo; + + let AddedComplexity = 2 in { + def : SVE_2_Op_Fp_Imm_Pat_Zero(NAME # "_ZERO_H")>; + def : SVE_2_Op_Fp_Imm_Pat_Zero(NAME # "_ZERO_H")>; + def : SVE_2_Op_Fp_Imm_Pat_Zero(NAME # "_ZERO_S")>; + def : SVE_2_Op_Fp_Imm_Pat_Zero(NAME # "_ZERO_S")>; + def : SVE_2_Op_Fp_Imm_Pat_Zero(NAME # "_ZERO_D")>; + def : SVE_2_Op_Fp_Imm_Pat_Zero(NAME # "_ZERO_D")>; + } +} + //===----------------------------------------------------------------------===// // SVE Floating Point Arithmetic - Unpredicated Group //===----------------------------------------------------------------------===// @@ -8371,3 +8429,4 @@ def : SVE_2_Op_Pred_All_Active_Pt(NAME # _UNDEF_S)>; def : SVE_2_Op_Pred_All_Active_Pt(NAME # _UNDEF_D)>; } + diff --git a/llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll b/llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll @@ -0,0 +1,1071 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +; +; FADD +; + +define @fadd_h_immhalf( %a) #0 { +; CHECK-LABEL: fadd_h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_h_immone( %a) #0 { +; CHECK-LABEL: fadd_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_4h_immhalf( %a) #0 { +; CHECK-LABEL: fadd_4h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_4h_immone( %a) #0 { +; CHECK-LABEL: fadd_4h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_2h_immhalf( %a) #0 { +; CHECK-LABEL: fadd_2h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_2h_immone( %a) #0 { +; CHECK-LABEL: fadd_2h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_s_immhalf( %a) #0 { +; CHECK-LABEL: fadd_s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_s_immone( %a) #0 { +; CHECK-LABEL: fadd_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_2s_immhalf( %a) #0 { +; CHECK-LABEL: fadd_2s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_2s_immone( %a) #0 { +; CHECK-LABEL: fadd_2s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + + +define @fadd_d_immhalf( %a) #0 { +; CHECK-LABEL: fadd_d_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fadd z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +define @fadd_d_immone( %a) #0 { +; CHECK-LABEL: fadd_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fadd z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fadd %a, %splat + ret %out +} + +; +; FMAX +; + +define @fmax_h_immzero( %a) #0 { +; CHECK-LABEL: fmax_h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv8f16( %a, %splat) + ret %out +} + +define @fmax_h_immone( %a) #0 { +; CHECK-LABEL: fmax_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv8f16( %a, %splat) + ret %out +} + +define @fmax_4h_immzero( %a) #0 { +; CHECK-LABEL: fmax_4h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv4f16( %a, %splat) + ret %out +} + +define @fmax_4h_immone( %a) #0 { +; CHECK-LABEL: fmax_4h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv4f16( %a, %splat) + ret %out +} + +define @fmax_2h_immzero( %a) #0 { +; CHECK-LABEL: fmax_2h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv2f16( %a, %splat) + ret %out +} + +define @fmax_2h_immone( %a) #0 { +; CHECK-LABEL: fmax_2h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv2f16( %a, %splat) + ret %out +} + +define @fmax_s_immzero( %a) #0 { +; CHECK-LABEL: fmax_s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv4f32( %a, %splat) + ret %out +} + +define @fmax_s_immone( %a) #0 { +; CHECK-LABEL: fmax_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv4f32( %a, %splat) + ret %out +} + +define @fmax_2s_immzero( %a) #0 { +; CHECK-LABEL: fmax_2s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv2f32( %a, %splat) + ret %out +} + +define @fmax_2s_immone( %a) #0 { +; CHECK-LABEL: fmax_2s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv2f32( %a, %splat) + ret %out +} + +define @fmax_d_immzero( %a) #0 { +; CHECK-LABEL: fmax_d_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv2f64( %a, %splat) + ret %out +} + +define @fmax_d_immone( %a) #0 { +; CHECK-LABEL: fmax_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maximum.nxv2f64( %a, %splat) + ret %out +} + +; +; FMAXNM +; + +define @fmaxnm_h_immzero( %a) #0 { +; CHECK-LABEL: fmaxnm_h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv8f16( %a, %splat) + ret %out +} + +define @fmaxnm_h_immone( %a) #0 { +; CHECK-LABEL: fmaxnm_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv8f16( %a, %splat) + ret %out +} + +define @fmaxnm_4h_immzero( %a) #0 { +; CHECK-LABEL: fmaxnm_4h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv4f16( %a, %splat) + ret %out +} + +define @fmaxnm_4h_immone( %a) #0 { +; CHECK-LABEL: fmaxnm_4h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv4f16( %a, %splat) + ret %out +} + +define @fmaxnm_2h_immzero( %a) #0 { +; CHECK-LABEL: fmaxnm_2h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv2f16( %a, %splat) + ret %out +} + +define @fmaxnm_2h_immone( %a) #0 { +; CHECK-LABEL: fmaxnm_2h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv2f16( %a, %splat) + ret %out +} + +define @fmaxnm_s_immzero( %a) #0 { +; CHECK-LABEL: fmaxnm_s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv4f32( %a, %splat) + ret %out +} + +define @fmaxnm_s_immone( %a) #0 { +; CHECK-LABEL: fmaxnm_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv4f32( %a, %splat) + ret %out +} + +define @fmaxnm_2s_immzero( %a) #0 { +; CHECK-LABEL: fmaxnm_2s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv2f32( %a, %splat) + ret %out +} + +define @fmaxnm_2s_immone( %a) #0 { +; CHECK-LABEL: fmaxnm_2s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv2f32( %a, %splat) + ret %out +} + +define @fmaxnm_d_immzero( %a) #0 { +; CHECK-LABEL: fmaxnm_d_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv2f64( %a, %splat) + ret %out +} + +define @fmaxnm_d_immone( %a) #0 { +; CHECK-LABEL: fmaxnm_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.maxnum.nxv2f64( %a, %splat) + ret %out +} + +; +; FMIN +; + +define @fmin_h_immzero( %a) #0 { +; CHECK-LABEL: fmin_h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv8f16( %a, %splat) + ret %out +} + +define @fmin_h_immone( %a) #0 { +; CHECK-LABEL: fmin_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv8f16( %a, %splat) + ret %out +} + +define @fmin_4h_immzero( %a) #0 { +; CHECK-LABEL: fmin_4h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv4f16( %a, %splat) + ret %out +} + +define @fmin_4h_immone( %a) #0 { +; CHECK-LABEL: fmin_4h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv4f16( %a, %splat) + ret %out +} + +define @fmin_2h_immzero( %a) #0 { +; CHECK-LABEL: fmin_2h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv2f16( %a, %splat) + ret %out +} + +define @fmin_2h_immone( %a) #0 { +; CHECK-LABEL: fmin_2h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv2f16( %a, %splat) + ret %out +} + +define @fmin_s_immzero( %a) #0 { +; CHECK-LABEL: fmin_s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv4f32( %a, %splat) + ret %out +} + +define @fmin_s_immone( %a) #0 { +; CHECK-LABEL: fmin_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv4f32( %a, %splat) + ret %out +} + +define @fmin_2s_immzero( %a) #0 { +; CHECK-LABEL: fmin_2s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv2f32( %a, %splat) + ret %out +} + +define @fmin_2s_immone( %a) #0 { +; CHECK-LABEL: fmin_2s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv2f32( %a, %splat) + ret %out +} + +define @fmin_d_immzero( %a) #0 { +; CHECK-LABEL: fmin_d_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv2f64( %a, %splat) + ret %out +} + +define @fmin_d_immone( %a) #0 { +; CHECK-LABEL: fmin_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minimum.nxv2f64( %a, %splat) + ret %out +} + +; +; FMINNM +; + +define @fminnm_h_immzero( %a) #0 { +; CHECK-LABEL: fminnm_h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv8f16( %a, %splat) + ret %out +} + +define @fminnm_h_immone( %a) #0 { +; CHECK-LABEL: fminnm_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv8f16( %a, %splat) + ret %out +} + +define @fminnm_4h_immzero( %a) #0 { +; CHECK-LABEL: fminnm_4h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv4f16( %a, %splat) + ret %out +} + +define @fminnm_4h_immone( %a) #0 { +; CHECK-LABEL: fminnm_4h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv4f16( %a, %splat) + ret %out +} + +define @fminnm_2h_immzero( %a) #0 { +; CHECK-LABEL: fminnm_2h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv2f16( %a, %splat) + ret %out +} + +define @fminnm_2h_immone( %a) #0 { +; CHECK-LABEL: fminnm_2h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv2f16( %a, %splat) + ret %out +} + +define @fminnm_s_immzero( %a) #0 { +; CHECK-LABEL: fminnm_s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv4f32( %a, %splat) + ret %out +} + +define @fminnm_s_immone( %a) #0 { +; CHECK-LABEL: fminnm_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv4f32( %a, %splat) + ret %out +} + +define @fminnm_2s_immzero( %a) #0 { +; CHECK-LABEL: fminnm_2s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv2f32( %a, %splat) + ret %out +} + +define @fminnm_2s_immone( %a) #0 { +; CHECK-LABEL: fminnm_2s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv2f32( %a, %splat) + ret %out +} + +define @fminnm_d_immzero( %a) #0 { +; CHECK-LABEL: fminnm_d_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv2f64( %a, %splat) + ret %out +} + +define @fminnm_d_immone( %a) #0 { +; CHECK-LABEL: fminnm_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.minnum.nxv2f64( %a, %splat) + ret %out +} + +; +; FMUL +; + +define @fmul_h_immhalf( %a) #0 { +; CHECK-LABEL: fmul_h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_h_immtwo( %a) #0 { +; CHECK-LABEL: fmul_h_immtwo: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd z0.h, z0.h, z0.h +; CHECK-NEXT: ret + %elt = insertelement undef, half 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_4h_immhalf( %a) #0 { +; CHECK-LABEL: fmul_4h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_4h_immtwo( %a) #0 { +; CHECK-LABEL: fmul_4h_immtwo: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z0.h +; CHECK-NEXT: ret + %elt = insertelement undef, half 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_2h_immhalf( %a) #0 { +; CHECK-LABEL: fmul_2h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_2h_immtwo( %a) #0 { +; CHECK-LABEL: fmul_2h_immtwo: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z0.h +; CHECK-NEXT: ret + %elt = insertelement undef, half 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_s_immhalf( %a) #0 { +; CHECK-LABEL: fmul_s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmul z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_s_immtwo( %a) #0 { +; CHECK-LABEL: fmul_s_immtwo: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd z0.s, z0.s, z0.s +; CHECK-NEXT: ret + %elt = insertelement undef, float 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_2s_immhalf( %a) #0 { +; CHECK-LABEL: fmul_2s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmul z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_2s_immtwo( %a) #0 { +; CHECK-LABEL: fmul_2s_immtwo: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z0.s +; CHECK-NEXT: ret + %elt = insertelement undef, float 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_d_immhalf( %a) #0 { +; CHECK-LABEL: fmul_d_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmul z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +define @fmul_d_immtwo( %a) #0 { +; CHECK-LABEL: fmul_d_immtwo: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd z0.d, z0.d, z0.d +; CHECK-NEXT: ret + %elt = insertelement undef, double 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fmul %a, %splat + ret %out +} + +; +; FSUB +; + +define @fsub_h_immhalf( %a) #0 { +; CHECK-LABEL: fsub_h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_h_immone( %a) #0 { +; CHECK-LABEL: fsub_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_4h_immhalf( %a) #0 { +; CHECK-LABEL: fsub_4h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_4h_immone( %a) #0 { +; CHECK-LABEL: fsub_4h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_2h_immhalf( %a) #0 { +; CHECK-LABEL: fsub_2h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_2h_immone( %a) #0 { +; CHECK-LABEL: fsub_2h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_s_immhalf( %a) #0 { +; CHECK-LABEL: fsub_s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fsub z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_s_immone( %a) #0 { +; CHECK-LABEL: fsub_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fsub z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_2s_immhalf( %a) #0 { +; CHECK-LABEL: fsub_2s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fsub z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_2s_immone( %a) #0 { +; CHECK-LABEL: fsub_2s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fsub z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_d_immhalf( %a) #0 { +; CHECK-LABEL: fsub_d_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fsub z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +define @fsub_d_immone( %a) #0 { +; CHECK-LABEL: fsub_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fsub z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = fsub %a, %splat + ret %out +} + +;; Arithmetic intrinsic declarations + +declare @llvm.maximum.nxv8f16(, ) +declare @llvm.maximum.nxv4f16(, ) +declare @llvm.maximum.nxv2f16(, ) +declare @llvm.maximum.nxv4f32(, ) +declare @llvm.maximum.nxv2f32(, ) +declare @llvm.maximum.nxv2f64(, ) + +declare @llvm.maxnum.nxv8f16(, ) +declare @llvm.maxnum.nxv4f16(, ) +declare @llvm.maxnum.nxv2f16(, ) +declare @llvm.maxnum.nxv4f32(, ) +declare @llvm.maxnum.nxv2f32(, ) +declare @llvm.maxnum.nxv2f64(, ) + +declare @llvm.minimum.nxv8f16(, ) +declare @llvm.minimum.nxv4f16(, ) +declare @llvm.minimum.nxv2f16(, ) +declare @llvm.minimum.nxv4f32(, ) +declare @llvm.minimum.nxv2f32(, ) +declare @llvm.minimum.nxv2f64(, ) + +declare @llvm.minnum.nxv8f16(, ) +declare @llvm.minnum.nxv4f16(, ) +declare @llvm.minnum.nxv2f16(, ) +declare @llvm.minnum.nxv4f32(, ) +declare @llvm.minnum.nxv2f32(, ) +declare @llvm.minnum.nxv2f64(, ) + +attributes #0 = { "target-features"="+sve" } +attributes #1 = { "target-features"="+sve,+use-experimental-zeroing-pseudos" } diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-imm.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-imm.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-imm.ll @@ -0,0 +1,1309 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define @fadd_h_immhalf( %pg, %a) #0 { +; CHECK-LABEL: fadd_h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv8f16( %pg, + %a, + %splat) + ret %out +} + + +define @fadd_h_immhalf_zero( %pg, %a) #1 { +; CHECK-LABEL: fadd_h_immhalf_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fadd_h_immone( %pg, %a) #0 { +; CHECK-LABEL: fadd_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fadd_h_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fadd_h_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fadd z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fadd_s_immhalf( %pg, %a) #0 { +; CHECK-LABEL: fadd_s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fadd_s_immhalf_zero( %pg, %a) #1 { +; CHECK-LABEL: fadd_s_immhalf_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fadd_s_immone( %pg, %a) #0 { +; CHECK-LABEL: fadd_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fadd_s_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fadd_s_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fadd z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fadd_d_immhalf( %pg, %a) #0 { +; CHECK-LABEL: fadd_d_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fadd_d_immhalf_zero( %pg, %a) #1 { +; CHECK-LABEL: fadd_d_immhalf_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fadd z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fadd_d_immone( %pg, %a) #0 { +; CHECK-LABEL: fadd_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fadd_d_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fadd_d_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fadd z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fadd.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fmax_h_immzero( %pg, %a) #0 { +; CHECK-LABEL: fmax_h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fmax_h_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fmax_h_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fmax_h_immone( %pg, %a) #0 { +; CHECK-LABEL: fmax_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fmax_h_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fmax_h_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fmax_s_immzero( %pg, %a) #0 { +; CHECK-LABEL: fmax_s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fmax_s_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fmax_s_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fmax_s_immone( %pg, %a) #0 { +; CHECK-LABEL: fmax_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fmax_s_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fmax_s_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fmax_d_immzero( %pg, %a) #0 { +; CHECK-LABEL: fmax_d_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fmax z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fmax_d_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fmax_d_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fmax z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fmax_d_immone( %pg, %a) #0 { +; CHECK-LABEL: fmax_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fmax z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fmax_d_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fmax_d_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fmax z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmax.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fmaxnm_h_immzero( %pg, %a) #0 { +; CHECK-LABEL: fmaxnm_h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fmaxnm_h_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fmaxnm_h_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fmaxnm_h_immone( %pg, %a) #0 { +; CHECK-LABEL: fmaxnm_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fmaxnm_h_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fmaxnm_h_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fmaxnm_s_immzero( %pg, %a) #0 { +; CHECK-LABEL: fmaxnm_s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fmaxnm_s_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fmaxnm_s_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fmaxnm_s_immone( %pg, %a) #0 { +; CHECK-LABEL: fmaxnm_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fmaxnm_s_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fmaxnm_s_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fmaxnm_d_immzero( %pg, %a) #0 { +; CHECK-LABEL: fmaxnm_d_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fmaxnm_d_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fmaxnm_d_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fmaxnm_d_immone( %pg, %a) #0 { +; CHECK-LABEL: fmaxnm_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fmaxnm_d_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fmaxnm_d_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fmin_h_immzero( %pg, %a) #0 { +; CHECK-LABEL: fmin_h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fmin_h_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fmin_h_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fmin_h_immone( %pg, %a) #0 { +; CHECK-LABEL: fmin_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fmin_h_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fmin_h_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fmin_s_immzero( %pg, %a) #0 { +; CHECK-LABEL: fmin_s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fmin_s_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fmin_s_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fmin_s_immone( %pg, %a) #0 { +; CHECK-LABEL: fmin_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fmin_s_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fmin_s_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fmin_d_immzero( %pg, %a) #0 { +; CHECK-LABEL: fmin_d_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fmin z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fmin_d_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fmin_d_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fmin z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fmin_d_immone( %pg, %a) #0 { +; CHECK-LABEL: fmin_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fmin z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fmin_d_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fmin_d_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fmin z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmin.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fminnm_h_immzero( %pg, %a) #0 { +; CHECK-LABEL: fminnm_h_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fminnm_h_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fminnm_h_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fminnm_h_immone( %pg, %a) #0 { +; CHECK-LABEL: fminnm_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fminnm_h_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fminnm_h_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fminnm_s_immzero( %pg, %a) #0 { +; CHECK-LABEL: fminnm_s_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fminnm_s_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fminnm_s_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fminnm_s_immone( %pg, %a) #0 { +; CHECK-LABEL: fminnm_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fminnm_s_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fminnm_s_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fminnm_d_immzero( %pg, %a) #0 { +; CHECK-LABEL: fminnm_d_immzero: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fminnm_d_immzero_zero( %pg, %a) #1 { +; CHECK-LABEL: fminnm_d_immzero_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, #0.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fminnm_d_immone( %pg, %a) #0 { +; CHECK-LABEL: fminnm_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fminnm_d_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fminnm_d_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fminnm.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fmul_h_immhalf( %pg, %a) #0 { +; CHECK-LABEL: fmul_h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fmul_h_immhalf_zero( %pg, %a) #1 { +; CHECK-LABEL: fmul_h_immhalf_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fmul z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fmul_h_immtwo( %pg, %a) #0 { +; CHECK-LABEL: fmul_h_immtwo: +; CHECK: // %bb.0: +; CHECK-NEXT: fmul z0.h, p0/m, z0.h, #2.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fmul_h_immtwo_zero( %pg, %a) #1 { +; CHECK-LABEL: fmul_h_immtwo_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fmul z0.h, p0/m, z0.h, #2.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fmul_s_immhalf( %pg, %a) #0 { +; CHECK-LABEL: fmul_s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: fmul z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fmul_s_immhalf_zero( %pg, %a) #1 { +; CHECK-LABEL: fmul_s_immhalf_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fmul z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fmul_s_immtwo( %pg, %a) #0 { +; CHECK-LABEL: fmul_s_immtwo: +; CHECK: // %bb.0: +; CHECK-NEXT: fmul z0.s, p0/m, z0.s, #2.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fmul_s_immtwo_zero( %pg, %a) #1 { +; CHECK-LABEL: fmul_s_immtwo_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fmul z0.s, p0/m, z0.s, #2.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fmul_d_immhalf( %pg, %a) #0 { +; CHECK-LABEL: fmul_d_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: fmul z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fmul_d_immhalf_zero( %pg, %a) #1 { +; CHECK-LABEL: fmul_d_immhalf_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fmul z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fmul_d_immtwo( %pg, %a) #0 { +; CHECK-LABEL: fmul_d_immtwo: +; CHECK: // %bb.0: +; CHECK-NEXT: fmul z0.d, p0/m, z0.d, #2.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fmul_d_immtwo_zero( %pg, %a) #1 { +; CHECK-LABEL: fmul_d_immtwo_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fmul z0.d, p0/m, z0.d, #2.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 2.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fmul.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fsub_h_immhalf( %pg, %a) #0 { +; CHECK-LABEL: fsub_h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fsub_h_immhalf_zero( %pg, %a) #1 { +; CHECK-LABEL: fsub_h_immhalf_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fsub_h_immone( %pg, %a) #0 { +; CHECK-LABEL: fsub_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv8f16( %pg, + %a, + %splat) + ret %out +} + +define @fsub_h_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fsub_h_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fsub z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fsub_s_immhalf( %pg, %a) #0 { +; CHECK-LABEL: fsub_s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: fsub z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fsub_s_immhalf_zero( %pg, %a) #1 { +; CHECK-LABEL: fsub_s_immhalf_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fsub z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fsub_s_immone( %pg, %a) #0 { +; CHECK-LABEL: fsub_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fsub z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv4f32( %pg, + %a, + %splat) + ret %out +} + +define @fsub_s_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fsub_s_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fsub z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fsub_d_immhalf( %pg, %a) #0 { +; CHECK-LABEL: fsub_d_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: fsub z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fsub_d_immhalf_zero( %pg, %a) #1 { +; CHECK-LABEL: fsub_d_immhalf_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fsub z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fsub_d_immone( %pg, %a) #0 { +; CHECK-LABEL: fsub_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: fsub z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv2f64( %pg, + %a, + %splat) + ret %out +} + +define @fsub_d_immone_zero( %pg, %a) #1 { +; CHECK-LABEL: fsub_d_immone_zero: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fsub z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsub.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fsubr_h_immhalf( %pg, %a) #1 { +; CHECK-LABEL: fsubr_h_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, half 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsubr.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fsubr_h_immone( %pg, %a) #1 { +; CHECK-LABEL: fsubr_h_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.h, p0/z, z0.h +; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, half 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsubr.nxv8f16( %pg, + %a_z, + %splat) + ret %out +} + +define @fsubr_s_immhalf( %pg, %a) #1 { +; CHECK-LABEL: fsubr_s_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, float 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsubr.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fsubr_s_immone( %pg, %a) #1 { +; CHECK-LABEL: fsubr_s_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.s, p0/z, z0.s +; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, float 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsubr.nxv4f32( %pg, + %a_z, + %splat) + ret %out +} + +define @fsubr_d_immhalf( %pg, %a) #1 { +; CHECK-LABEL: fsubr_d_immhalf: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fsubr z0.d, p0/m, z0.d, #0.5 +; CHECK-NEXT: ret + %elt = insertelement undef, double 0.500000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsubr.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + +define @fsubr_d_immone( %pg, %a) #1 { +; CHECK-LABEL: fsubr_d_immone: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0.d, p0/z, z0.d +; CHECK-NEXT: fsubr z0.d, p0/m, z0.d, #1.0 +; CHECK-NEXT: ret + %elt = insertelement undef, double 1.000000e+00, i32 0 + %splat = shufflevector %elt, undef, zeroinitializer + %a_z = select %pg, %a, zeroinitializer + %out = call @llvm.aarch64.sve.fsubr.nxv2f64( %pg, + %a_z, + %splat) + ret %out +} + + +;; Arithmetic intrinsic declarations + +declare @llvm.aarch64.sve.fadd.nxv8f16(, , ) +declare @llvm.aarch64.sve.fadd.nxv4f32(, , ) +declare @llvm.aarch64.sve.fadd.nxv2f64(, , ) + +declare @llvm.aarch64.sve.fmax.nxv8f16(, , ) +declare @llvm.aarch64.sve.fmax.nxv4f32(, , ) +declare @llvm.aarch64.sve.fmax.nxv2f64(, , ) + +declare @llvm.aarch64.sve.fmaxnm.nxv8f16(, , ) +declare @llvm.aarch64.sve.fmaxnm.nxv4f32(, , ) +declare @llvm.aarch64.sve.fmaxnm.nxv2f64(, , ) + +declare @llvm.aarch64.sve.fmin.nxv8f16(, , ) +declare @llvm.aarch64.sve.fmin.nxv4f32(, , ) +declare @llvm.aarch64.sve.fmin.nxv2f64(, , ) + +declare @llvm.aarch64.sve.fminnm.nxv8f16(, , ) +declare @llvm.aarch64.sve.fminnm.nxv4f32(, , ) +declare @llvm.aarch64.sve.fminnm.nxv2f64(, , ) + +declare @llvm.aarch64.sve.fmul.nxv8f16(, , ) +declare @llvm.aarch64.sve.fmul.nxv4f32(, , ) +declare @llvm.aarch64.sve.fmul.nxv2f64(, , ) + +declare @llvm.aarch64.sve.fsub.nxv8f16(, , ) +declare @llvm.aarch64.sve.fsub.nxv4f32(, , ) +declare @llvm.aarch64.sve.fsub.nxv2f64(, , ) + +declare @llvm.aarch64.sve.fsubr.nxv8f16(, , ) +declare @llvm.aarch64.sve.fsubr.nxv4f32(, , ) +declare @llvm.aarch64.sve.fsubr.nxv2f64(, , ) + +attributes #0 = { "target-features"="+sve" } +attributes #1 = { "target-features"="+sve,+use-experimental-zeroing-pseudos" }