Index: llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
+++ llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
@@ -197,6 +197,26 @@
       return buildConstant(DstOps[0], *Cst);
     break;
   }
+  case TargetOpcode::G_FADD:
+  case TargetOpcode::G_FSUB:
+  case TargetOpcode::G_FMUL:
+  case TargetOpcode::G_FDIV:
+  case TargetOpcode::G_FREM:
+  case TargetOpcode::G_FMINNUM:
+  case TargetOpcode::G_FMAXNUM:
+  case TargetOpcode::G_FMINNUM_IEEE:
+  case TargetOpcode::G_FMAXNUM_IEEE:
+  case TargetOpcode::G_FMINIMUM:
+  case TargetOpcode::G_FMAXIMUM:
+  case TargetOpcode::G_FCOPYSIGN: {
+    // Try to constant fold these.
+    assert(SrcOps.size() == 2 && "Invalid sources");
+    assert(DstOps.size() == 1 && "Invalid dsts");
+    if (Optional<APFloat> Cst = ConstantFoldFPBinOp(
+            Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI()))
+      return buildFConstant(DstOps[0], *Cst);
+    break;
+  }
   case TargetOpcode::G_SEXT_INREG: {
     assert(DstOps.size() == 1 && "Invalid dst ops");
     assert(SrcOps.size() == 2 && "Invalid src ops");
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
@@ -1002,12 +1002,9 @@
     ; CHECK: %reg:_(s32) = COPY $vgpr0
     ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
-    ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
-    ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
-    ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD %two, %sixteen
-    ; CHECK: [[FADD1:%[0-9]+]]:_(s32) = G_FADD %four, %sixteen
-    ; CHECK: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[FADD]], [[FADD1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.800000e+01
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+01
+    ; CHECK: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
     ; CHECK: S_ENDPGM 0, implicit %fadd(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1031,12 +1028,9 @@
     ; CHECK: %reg:_(s32) = COPY $vgpr0
     ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
-    ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
-    ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
-    ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD %sixteen, %two
-    ; CHECK: [[FADD1:%[0-9]+]]:_(s32) = G_FADD %sixteen, %four
-    ; CHECK: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[FADD]], [[FADD1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.800000e+01
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+01
+    ; CHECK: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
     ; CHECK: S_ENDPGM 0, implicit %fadd(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1060,12 +1054,9 @@
     ; CHECK: %reg:_(s32) = COPY $vgpr0
     ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
-    ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
-    ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
-    ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB %two, %sixteen
-    ; CHECK: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB %four, %sixteen
-    ; CHECK: %fsub:_(s32) = nnan G_SELECT %cond(s1), [[FSUB]], [[FSUB1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.400000e+01
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.200000e+01
+    ; CHECK: %fsub:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
     ; CHECK: S_ENDPGM 0, implicit %fsub(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1089,12 +1080,9 @@
     ; CHECK: %reg:_(s32) = COPY $vgpr0
     ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
-    ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
-    ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
-    ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL %two, %sixteen
-    ; CHECK: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL %four, %sixteen
-    ; CHECK: %fmul:_(s32) = nnan G_SELECT %cond(s1), [[FMUL]], [[FMUL1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
+    ; CHECK: %fmul:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
     ; CHECK: S_ENDPGM 0, implicit %fmul(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1118,12 +1106,9 @@
     ; CHECK: %reg:_(s32) = COPY $vgpr0
     ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
-    ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
-    ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
-    ; CHECK: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV %two, %sixteen
-    ; CHECK: [[FDIV1:%[0-9]+]]:_(s32) = G_FDIV %four, %sixteen
-    ; CHECK: %fdiv:_(s32) = nnan G_SELECT %cond(s1), [[FDIV]], [[FDIV1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.250000e-01
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.500000e-01
+    ; CHECK: %fdiv:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
     ; CHECK: S_ENDPGM 0, implicit %fdiv(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1149,10 +1134,7 @@
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
     ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
     ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
-    ; CHECK: [[FREM:%[0-9]+]]:_(s32) = G_FREM %two, %sixteen
-    ; CHECK: [[FREM1:%[0-9]+]]:_(s32) = G_FREM %four, %sixteen
-    ; CHECK: %frem:_(s32) = nnan G_SELECT %cond(s1), [[FREM]], [[FREM1]]
+    ; CHECK: %frem:_(s32) = nnan G_SELECT %cond(s1), %two, %four
     ; CHECK: S_ENDPGM 0, implicit %frem(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1207,10 +1189,7 @@
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
     ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
     ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
-    ; CHECK: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM %two, %sixteen
-    ; CHECK: [[FMINNUM1:%[0-9]+]]:_(s32) = G_FMINNUM %four, %sixteen
-    ; CHECK: %fminnum:_(s32) = nnan G_SELECT %cond(s1), [[FMINNUM]], [[FMINNUM1]]
+    ; CHECK: %fminnum:_(s32) = nnan G_SELECT %cond(s1), %two, %four
     ; CHECK: S_ENDPGM 0, implicit %fminnum(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1263,11 +1242,9 @@
     ; CHECK: %reg:_(s32) = COPY $vgpr0
     ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
-    ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
     ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %select:_(s32) = G_SELECT %cond(s1), %two, %four
     ; CHECK: %three:_(s32) = G_FCONSTANT float 3.000000e+00
-    ; CHECK: %fmaxnum:_(s32) = nnan G_FMAXNUM %select, %three
+    ; CHECK: %fmaxnum:_(s32) = nnan G_SELECT %cond(s1), %three, %four
     ; CHECK: S_ENDPGM 0, implicit %fmaxnum(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1293,9 +1270,10 @@
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
     ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
     ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %select:_(s32) = G_SELECT %cond(s1), %two, %four
     ; CHECK: %three:_(s32) = G_FCONSTANT float 3.000000e+00
-    ; CHECK: %fmaxnum_ieee:_(s32) = nnan G_FMAXNUM_IEEE %select, %three
+    ; CHECK: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE %two, %three
+    ; CHECK: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE %four, %three
+    ; CHECK: %fmaxnum_ieee:_(s32) = nnan G_SELECT %cond(s1), [[FMAXNUM_IEEE]], [[FMAXNUM_IEEE1]]
     ; CHECK: S_ENDPGM 0, implicit %fmaxnum_ieee(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1321,9 +1299,7 @@
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
     ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
     ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %select:_(s32) = G_SELECT %cond(s1), %two, %four
-    ; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
-    ; CHECK: %fminimum:_(s32) = nnan G_FMINIMUM %select, %sixteen
+    ; CHECK: %fminimum:_(s32) = nnan G_SELECT %cond(s1), %two, %four
     ; CHECK: S_ENDPGM 0, implicit %fminimum(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1347,11 +1323,9 @@
     ; CHECK: %reg:_(s32) = COPY $vgpr0
     ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
     ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
-    ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
     ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
-    ; CHECK: %select:_(s32) = G_SELECT %cond(s1), %two, %four
     ; CHECK: %three:_(s32) = G_FCONSTANT float 3.000000e+00
-    ; CHECK: %fmaximum:_(s32) = nnan G_FMAXIMUM %select, %three
+    ; CHECK: %fmaximum:_(s32) = nnan G_SELECT %cond(s1), %three, %four
     ; CHECK: S_ENDPGM 0, implicit %fmaximum(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0