diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,5 +17,15 @@
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+// Zbr extension
+TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11167,7 +11167,7 @@
   "calling %0 is a violation of trusted computing base '%1'">,
   InGroup<DiagGroup<"tcb-enforcement">>;
 
-// RISC-V V-extension
-def err_riscvv_builtin_requires_v : Error<
-   "builtin requires 'V' extension support to be enabled">;
+// RISC-V builtin required extension warning
+def err_riscv_builtin_requires_extension : Error<
+  "builtin requires %0 extension support to be enabled">;
 } // end of sema component.
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -17858,6 +17858,44 @@
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
 #include "clang/Basic/riscv_vector_builtin_cg.inc"
+
+  // Zbr
+  case RISCV::BI__builtin_riscv_crc32_b:
+    ID = Intrinsic::riscv_crc32_b;
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32_h:
+    ID = Intrinsic::riscv_crc32_h;
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32_w:
+    ID = Intrinsic::riscv_crc32_w;
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_b:
+    ID = Intrinsic::riscv_crc32c_b;
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_h:
+    ID = Intrinsic::riscv_crc32c_h;
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_w:
+    ID = Intrinsic::riscv_crc32c_w;
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32_d:
+    ID = Intrinsic::riscv_crc32_d;
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_d:
+    ID = Intrinsic::riscv_crc32c_d;
+    IntrinsicTypes = {ResultType, Ops[0]->getType()};
+    break;
+  default: {
+    llvm_unreachable("unexpected builtin ID");
+    return nullptr;
+  } // default
   }
 
   assert(ID != Intrinsic::not_intrinsic);
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3395,13 +3395,28 @@
                                          CallExpr *TheCall) {
   // CodeGenFunction can also detect this, but this gives a better error
   // message.
+  bool miss_feature_error = false;
+  SmallVector<StringRef> ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  if (Features.find("experimental-v") != StringRef::npos &&
-      !TI.hasFeature("experimental-v"))
-    return Diag(TheCall->getBeginLoc(), diag::err_riscvv_builtin_requires_v)
-           << TheCall->getSourceRange();
-
-  return false;
+  StringRef(Features).split(ReqFeatures, ',');
+  
+  // Check if each required feature is included in TargetInfo
+  for (size_t i = 0; i < ReqFeatures.size(); i++) {
+    if (!TI.hasFeature(ReqFeatures[i])) {
+      
+      // Make message like "experimental-zbr" to "Zbr"
+      ReqFeatures[i].consume_front("experimental-");
+      std::string FeatureStr = ReqFeatures[i].str();
+      FeatureStr[0] = std::toupper(FeatureStr[0]);
+      
+      // Error message
+      miss_feature_error = true;
+      Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
+      << TheCall->getSourceRange() << StringRef(FeatureStr);
+    }
+  }
+
+  return miss_feature_error;
 }
 
 bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c
@@ -0,0 +1,75 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbr -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBR
+
+// RV32ZBR-LABEL: @crc32b(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.b.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32b(long a) {
+  return __builtin_riscv_crc32_b(a);
+}
+
+// RV32ZBR-LABEL: @crc32h(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.h.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32h(long a) {
+  return __builtin_riscv_crc32_h(a);
+}
+
+// RV32ZBR-LABEL: @crc32w(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.w.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32w(long a) {
+  return __builtin_riscv_crc32_w(a);
+}
+
+// RV32ZBR-LABEL: @crc32cb(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.b.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32cb(long a) {
+  return __builtin_riscv_crc32c_b(a);
+}
+
+// RV32ZBR-LABEL: @crc32ch(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.h.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32ch(long a) {
+  return __builtin_riscv_crc32c_h(a);
+}
+
+// RV32ZBR-LABEL: @crc32cw(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.w.i32.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32cw(long a) {
+  return __builtin_riscv_crc32c_w(a);
+}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c
@@ -0,0 +1,99 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbr -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBR
+
+// RV64ZBR-LABEL: @crc32b(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.b.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32b(long a) {
+  return __builtin_riscv_crc32_b(a);
+}
+
+// RV64ZBR-LABEL: @crc32h(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.h.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32h(long a) {
+  return __builtin_riscv_crc32_h(a);
+}
+
+// RV64ZBR-LABEL: @crc32w(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.w.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32w(long a) {
+  return __builtin_riscv_crc32_w(a);
+}
+
+// RV64ZBR-LABEL: @crc32cb(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.b.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32cb(long a) {
+  return __builtin_riscv_crc32c_b(a);
+}
+
+// RV64ZBR-LABEL: @crc32ch(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.h.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32ch(long a) {
+  return __builtin_riscv_crc32c_h(a);
+}
+
+// RV64ZBR-LABEL: @crc32cw(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.w.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32cw(long a) {
+  return __builtin_riscv_crc32c_w(a);
+}
+
+// RV64ZBR-LABEL: @crc32d(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.d.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32d(long a) {
+  return __builtin_riscv_crc32_d(a);
+}
+
+// RV64ZBR-LABEL: @crc32cd(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.d.i64.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32cd(long a) {
+  return __builtin_riscv_crc32c_d(a);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -10,6 +10,27 @@
 //
 //===----------------------------------------------------------------------===//
 
+//===----------------------------------------------------------------------===//
+// RISC-V Bitmanip (Bit Manipulation) Extension
+// Zbr extension part
+
+let TargetPrefix = "riscv" in {
+  
+    class BitMan_GPR_Intrinsics
+        : Intrinsic<[llvm_any_ty], [llvm_any_ty],
+                    [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+  
+    def int_riscv_crc32_b : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_h : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_w : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_b : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_h : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_w : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_d : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_d : BitMan_GPR_Intrinsics;
+
+} // TargetPrefix = "riscv"
+
 //===----------------------------------------------------------------------===//
 // Atomics
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -840,6 +840,8 @@
 
 /// Generic pattern classes
 
+class PatGpr<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
 class PatGprGpr<SDPatternOperator OpNode, RVInst Inst>
     : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
 class PatGprSimm12<SDPatternOperator OpNode, RVInstI Inst>
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -874,3 +874,17 @@
                    (SRLIWPat GPR:$rs1, (i64 16)))),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbr] in {
+def : PatGpr<int_riscv_crc32_b, CRC32B>;
+def : PatGpr<int_riscv_crc32_h, CRC32H>;
+def : PatGpr<int_riscv_crc32_w, CRC32W>;
+def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
+def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
+def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
+} // Predicates = [HasStdExtZbr]
+
+let Predicates = [HasStdExtZbr, IsRV64] in {
+def : PatGpr<int_riscv_crc32_d, CRC32D>;
+def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
+} // Predicates = [HasStdExtZbr, IsRV64]
diff --git a/llvm/test/CodeGen/RISCV/rv32zbr.ll b/llvm/test/CodeGen/RISCV/rv32zbr.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv32zbr.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBR
+
+declare i32 @llvm.riscv.crc32.b.i32(i32)
+
+define i32 @crc32b(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32b:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32.b a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.h.i32(i32)
+
+define i32 @crc32h(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32h:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32.h a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.w.i32(i32)
+
+define i32 @crc32w(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32w:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32.w a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32.w.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.b.i32(i32)
+
+define i32 @crc32cb(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32cb:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32c.b a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32c.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.h.i32(i32)
+
+define i32 @crc32ch(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32ch:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32c.h a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32c.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.w.i32(i32)
+
+define i32 @crc32cw(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32cw:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32c.w a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32c.w.i32(i32 %a)
+ ret i32 %tmp
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64zbr.ll b/llvm/test/CodeGen/RISCV/rv64zbr.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64zbr.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBR
+
+declare i64 @llvm.riscv.crc32.b.i64(i64)
+
+define i64 @crc32b(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32b:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.b a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.h.i64(i64)
+
+define i64 @crc32h(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32h:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.h a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.w.i64(i64)
+
+define i64 @crc32w(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32w:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.w a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.b.i64(i64)
+
+define i64 @crc32cb(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cb:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.b a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.h.i64(i64)
+
+define i64 @crc32ch(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32ch:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.h a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.w.i64(i64)
+
+define i64 @crc32cw(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cw:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.w a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.d.i64(i64)
+
+define i64 @crc32d(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32d:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.d a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.d.i64(i64)
+
+define i64 @crc32cd(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cd:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.d a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a)
+ ret i64 %tmp
+}