diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -620,6 +620,14 @@
   /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
   /// this override can be removed.
   bool mergeStoresAfterLegalization(EVT VT) const override;
+
+  /// Disable normalizing
+  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
+  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
+  /// RISCV doesn't have flags so it's better to perform the and/or in a GPR.
+  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
+    return false;
+  };
 };
 
 namespace RISCV {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -963,9 +963,6 @@
   // Jumps are expensive, compared to logic
   setJumpIsExpensive();
 
-  // We can use any register for comparisons
-  setHasMultipleConditionRegisters();
-
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::SUB);
   setTargetDAGCombine(ISD::AND);
diff --git a/llvm/test/CodeGen/RISCV/sink-icmp.ll b/llvm/test/CodeGen/RISCV/sink-icmp.ll
--- a/llvm/test/CodeGen/RISCV/sink-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/sink-icmp.ll
@@ -10,8 +10,7 @@
 ; RV32-NEXT:    lh a0, 0(a0)
 ; RV32-NEXT:    bltz a0, .LBB0_3
 ; RV32-NEXT:  # %bb.1: # %.LBB0_1
-; RV32-NEXT:    seqz a1, a1
-; RV32-NEXT:    bnez a1, .LBB0_3
+; RV32-NEXT:    beqz a1, .LBB0_3
 ; RV32-NEXT:  # %bb.2: # %.LBB0_2
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB0_3: # %return
@@ -23,8 +22,7 @@
 ; RV64-NEXT:    lh a0, 0(a0)
 ; RV64-NEXT:    bltz a0, .LBB0_3
 ; RV64-NEXT:  # %bb.1: # %.LBB0_1
-; RV64-NEXT:    seqz a1, a1
-; RV64-NEXT:    bnez a1, .LBB0_3
+; RV64-NEXT:    beqz a1, .LBB0_3
 ; RV64-NEXT:  # %bb.2: # %.LBB0_2
 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB0_3: # %return