diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -416,11 +416,8 @@ ReplaceNode(Node, New.getNode()); return; } - int64_t Imm = ConstNode->getSExtValue(); - if (XLenVT == MVT::i64) { - ReplaceNode(Node, selectImm(CurDAG, DL, Imm, XLenVT)); - return; - } + ReplaceNode(Node, selectImm(CurDAG, DL, ConstNode->getSExtValue(), XLenVT)); + return; break; } case ISD::FrameIndex: { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -308,21 +308,6 @@ def AddrFI : ComplexPattern; def BaseAddr : ComplexPattern; -// Extract least significant 12 bits from an immediate value and sign extend -// them. -def LO12Sext : SDNodeXFormgetTargetConstant(SignExtend64<12>(N->getZExtValue()), - SDLoc(N), N->getValueType(0)); -}]>; - -// Extract the most significant 20 bits from an immediate value. Add 1 if bit -// 11 is 1, to compensate for the low 12 bits in the matching immediate addi -// or ld/st being negative. -def HI20 : SDNodeXFormgetTargetConstant(((N->getZExtValue()+0x800) >> 12) & 0xfffff, - SDLoc(N), N->getValueType(0)); -}]>; - // Return the negation of an immediate value. def NegImm : SDNodeXFormgetTargetConstant(-N->getSExtValue(), SDLoc(N), @@ -874,13 +859,6 @@ return MatchSLLIUW(N); }]>; -/// Immediates - -def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>; -def : Pat<(simm32hi20:$imm), (LUI (HI20 imm:$imm))>; -def : Pat<(i32 (simm32:$imm)), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>, - Requires<[IsRV32]>; - /// Simple arithmetic operations def : PatGprGpr;