diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -915,8 +915,10 @@ /// \return the target-provided register class name const char *getRegisterClassName(unsigned ClassID) const; + enum RegisterKind { RGK_Scalar, RGK_FixedWidthVector, RGK_ScalableVector }; + /// \return The width of the largest scalar or vector register type. - unsigned getRegisterBitWidth(bool Vector) const; + TypeSize getRegisterBitWidth(RegisterKind K) const; /// \return The width of the smallest vector register type. unsigned getMinVectorRegisterBitWidth() const; @@ -1510,7 +1512,7 @@ virtual unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const = 0; virtual const char *getRegisterClassName(unsigned ClassID) const = 0; - virtual unsigned getRegisterBitWidth(bool Vector) const = 0; + virtual TypeSize getRegisterBitWidth(RegisterKind K) const = 0; virtual unsigned getMinVectorRegisterBitWidth() = 0; virtual Optional getMaxVScale() const = 0; virtual bool shouldMaximizeVectorBandwidth(bool OptSize) const = 0; @@ -1932,8 +1934,8 @@ const char *getRegisterClassName(unsigned ClassID) const override { return Impl.getRegisterClassName(ClassID); } - unsigned getRegisterBitWidth(bool Vector) const override { - return Impl.getRegisterBitWidth(Vector); + TypeSize getRegisterBitWidth(RegisterKind K) const override { + return Impl.getRegisterBitWidth(K); } unsigned getMinVectorRegisterBitWidth() override { return Impl.getMinVectorRegisterBitWidth(); diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -370,7 +370,9 @@ } } - unsigned getRegisterBitWidth(bool Vector) const { return 32; } + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + return TypeSize::getFixed(32); + } unsigned getMinVectorRegisterBitWidth() const { return 128; } diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -570,7 +570,9 @@ /// \name Vector TTI Implementations /// @{ - unsigned getRegisterBitWidth(bool Vector) const { return 32; } + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + return TypeSize::getFixed(32); + } Optional getMaxVScale() const { return None; } diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -573,8 +573,9 @@ return TTIImpl->getRegisterClassName(ClassID); } -unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const { - return TTIImpl->getRegisterBitWidth(Vector); +TypeSize TargetTransformInfo::getRegisterBitWidth( + TargetTransformInfo::RegisterKind K) const { + return TTIImpl->getRegisterBitWidth(K); } unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const { diff --git a/llvm/lib/CodeGen/TypePromotion.cpp b/llvm/lib/CodeGen/TypePromotion.cpp --- a/llvm/lib/CodeGen/TypePromotion.cpp +++ b/llvm/lib/CodeGen/TypePromotion.cpp @@ -952,7 +952,8 @@ const TargetLowering *TLI = SubtargetInfo->getTargetLowering(); const TargetTransformInfo &TII = getAnalysis().getTTI(F); - RegisterBitWidth = TII.getRegisterBitWidth(false); + RegisterBitWidth = + TII.getRegisterBitWidth(TargetTransformInfo::RGK_Scalar).getFixedSize(); Ctx = &F.getParent()->getContext(); // Search up from icmps to try to promote their operands. diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -100,15 +100,19 @@ unsigned getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind); - unsigned getRegisterBitWidth(bool Vector) const { - if (Vector) { + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(64); + case TargetTransformInfo::RGK_FixedWidthVector: if (ST->hasSVE()) - return std::max(ST->getMinSVEVectorSizeInBits(), 128u); - if (ST->hasNEON()) - return 128; - return 0; + return TypeSize::getFixed( + std::max(ST->getMinSVEVectorSizeInBits(), 128u)); + return TypeSize::getFixed(ST->hasNEON() ? 128 : 0); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(ST->hasSVE() ? 128 : 0); } - return 64; + llvm_unreachable("Unsupported register kind"); } unsigned getMinVectorRegisterBitWidth() { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -121,7 +121,7 @@ unsigned getHardwareNumberOfRegisters(bool Vector) const; unsigned getNumberOfRegisters(bool Vector) const; unsigned getNumberOfRegisters(unsigned RCID) const; - unsigned getRegisterBitWidth(bool Vector) const; + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const; unsigned getMinVectorRegisterBitWidth() const; unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const; unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, @@ -243,7 +243,7 @@ TTI::PeelingPreferences &PP); unsigned getHardwareNumberOfRegisters(bool Vec) const; unsigned getNumberOfRegisters(bool Vec) const; - unsigned getRegisterBitWidth(bool Vector) const; + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const; unsigned getMinVectorRegisterBitWidth() const; unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const; bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -310,8 +310,17 @@ return getHardwareNumberOfRegisters(false) / NumVGPRs; } -unsigned GCNTTIImpl::getRegisterBitWidth(bool Vector) const { - return (Vector && ST->hasPackedFP32Ops()) ? 64 : 32; +TypeSize +GCNTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(32); + case TargetTransformInfo::RGK_FixedWidthVector: + return TypeSize::getFixed(ST->hasPackedFP32Ops() ? 64 : 32); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(0); + } + llvm_unreachable("Unsupported register kind"); } unsigned GCNTTIImpl::getMinVectorRegisterBitWidth() const { @@ -1223,8 +1232,9 @@ return getHardwareNumberOfRegisters(Vec); } -unsigned R600TTIImpl::getRegisterBitWidth(bool Vector) const { - return 32; +TypeSize +R600TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + return TypeSize::getFixed(32); } unsigned R600TTIImpl::getMinVectorRegisterBitWidth() const { diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -149,16 +149,17 @@ return 13; } - unsigned getRegisterBitWidth(bool Vector) const { - if (Vector) { - if (ST->hasNEON()) - return 128; - if (ST->hasMVEIntegerOps()) - return 128; - return 0; + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(32); + case TargetTransformInfo::RGK_FixedWidthVector: + return TypeSize::getFixed((ST->hasNEON() || ST->hasMVEIntegerOps()) ? 128 + : 0); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(0); } - - return 32; + llvm_unreachable("Unsupported register kind"); } unsigned getMaxInterleaveFactor(unsigned VF) { diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -81,7 +81,7 @@ unsigned getNumberOfRegisters(bool vector) const; unsigned getMaxInterleaveFactor(unsigned VF); - unsigned getRegisterBitWidth(bool Vector) const; + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; unsigned getMinVectorRegisterBitWidth() const; ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp @@ -98,8 +98,18 @@ return useHVX() ? 2 : 1; } -unsigned HexagonTTIImpl::getRegisterBitWidth(bool Vector) const { - return Vector ? getMinVectorRegisterBitWidth() : 32; +TypeSize +HexagonTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(32); + case TargetTransformInfo::RGK_FixedWidthVector: + return TypeSize::getFixed(getMinVectorRegisterBitWidth()); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(0); + } + + llvm_unreachable("Unsupported register kind"); } unsigned HexagonTTIImpl::getMinVectorRegisterBitWidth() const { @@ -162,7 +172,9 @@ VectorType *VecTy = cast(Src); unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize(); if (useHVX() && ST.isTypeForHVX(VecTy)) { - unsigned RegWidth = getRegisterBitWidth(true); + unsigned RegWidth = + getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) + .getFixedSize(); assert(RegWidth && "Non-zero vector register width expected"); // Cost of HVX loads. if (VecWidth % RegWidth == 0) diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h --- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h @@ -71,7 +71,9 @@ // Only <2 x half> should be vectorized, so always return 32 for the vector // register size. - unsigned getRegisterBitWidth(bool Vector) const { return 32; } + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + return TypeSize::getFixed(32); + } unsigned getMinVectorRegisterBitWidth() const { return 32; } // We don't want to prevent inlining because of target-cpu and -features diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -93,7 +93,7 @@ unsigned getNumberOfRegisters(unsigned ClassID) const; unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const; const char* getRegisterClassName(unsigned ClassID) const; - unsigned getRegisterBitWidth(bool Vector) const; + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; unsigned getCacheLineSize() const override; unsigned getPrefetchDistance() const override; unsigned getMaxInterleaveFactor(unsigned VF); diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -871,16 +871,18 @@ } } -unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) const { - if (Vector) { - if (ST->hasAltivec()) return 128; - return 0; +TypeSize +PPCTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(ST->isPPC64() ? 64 : 32); + case TargetTransformInfo::RGK_FixedWidthVector: + return TypeSize::getFixed(ST->hasAltivec() ? 128 : 0); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(0); } - if (ST->isPPC64()) - return 64; - return 32; - + llvm_unreachable("Unsupported register kind"); } unsigned PPCTTIImpl::getCacheLineSize() const { diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -62,7 +62,7 @@ /// @{ unsigned getNumberOfRegisters(unsigned ClassID) const; - unsigned getRegisterBitWidth(bool Vector) const; + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; unsigned getCacheLineSize() const override { return 256; } unsigned getPrefetchDistance() const override { return 4500; } diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp @@ -323,12 +323,18 @@ return 0; } -unsigned SystemZTTIImpl::getRegisterBitWidth(bool Vector) const { - if (!Vector) - return 64; - if (ST->hasVector()) - return 128; - return 0; +TypeSize +SystemZTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(64); + case TargetTransformInfo::RGK_FixedWidthVector: + return TypeSize::getFixed(ST->hasVector() ? 128 : 0); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(0); + } + + llvm_unreachable("Unsupported register kind"); } unsigned SystemZTTIImpl::getMinPrefetchStride(unsigned NumMemAccesses, diff --git a/llvm/lib/Target/VE/VETargetTransformInfo.h b/llvm/lib/Target/VE/VETargetTransformInfo.h --- a/llvm/lib/Target/VE/VETargetTransformInfo.h +++ b/llvm/lib/Target/VE/VETargetTransformInfo.h @@ -50,12 +50,18 @@ return 64; } - unsigned getRegisterBitWidth(bool Vector) const { - if (Vector) { + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(64); + case TargetTransformInfo::RGK_FixedWidthVector: // TODO report vregs once vector isel is stable. - return 0; + return TypeSize::getFixed(0); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(0); } - return 64; + + llvm_unreachable("Unsupported register kind"); } unsigned getMinVectorRegisterBitWidth() const { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h @@ -57,7 +57,7 @@ /// @{ unsigned getNumberOfRegisters(unsigned ClassID) const; - unsigned getRegisterBitWidth(bool Vector) const; + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; unsigned getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp @@ -36,11 +36,18 @@ return Result; } -unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const { - if (Vector && getST()->hasSIMD128()) - return 128; +TypeSize WebAssemblyTTIImpl::getRegisterBitWidth( + TargetTransformInfo::RegisterKind K) const { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(64); + case TargetTransformInfo::RGK_FixedWidthVector: + return TypeSize::getFixed(getST()->hasSIMD128() ? 128 : 64); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(0); + } - return 64; + llvm_unreachable("Unsupported register kind"); } unsigned WebAssemblyTTIImpl::getArithmeticInstrCost( diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -115,7 +115,7 @@ /// @{ unsigned getNumberOfRegisters(unsigned ClassID) const; - unsigned getRegisterBitWidth(bool Vector) const; + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; unsigned getLoadStoreVecRegBitWidth(unsigned AS) const; unsigned getMaxInterleaveFactor(unsigned VF); int getArithmeticInstrCost( diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -129,26 +129,30 @@ return 8; } -unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { +TypeSize +X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { unsigned PreferVectorWidth = ST->getPreferVectorWidth(); - if (Vector) { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); + case TargetTransformInfo::RGK_FixedWidthVector: if (ST->hasAVX512() && PreferVectorWidth >= 512) - return 512; + return TypeSize::getFixed(512); if (ST->hasAVX() && PreferVectorWidth >= 256) - return 256; + return TypeSize::getFixed(256); if (ST->hasSSE1() && PreferVectorWidth >= 128) - return 128; - return 0; + return TypeSize::getFixed(128); + return TypeSize::getFixed(0); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(0); } - if (ST->is64Bit()) - return 64; - - return 32; + llvm_unreachable("Unsupported register kind"); } unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { - return getRegisterBitWidth(true); + return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) + .getFixedSize(); } unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { diff --git a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp --- a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp +++ b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp @@ -413,7 +413,9 @@ /// \p VT * N. unsigned getNumOps(Type *ST, unsigned N) { return std::ceil((ST->getPrimitiveSizeInBits() * N).getFixedSize() / - double(TTI.getRegisterBitWidth(true))); + double(TTI.getRegisterBitWidth( + TargetTransformInfo::RGK_FixedWidthVector) + .getFixedSize())); } /// Return the set of vectors that a matrix value is lowered to. @@ -1013,7 +1015,8 @@ const MatrixTy &B, bool AllowContraction, IRBuilder<> &Builder, bool isTiled) { const unsigned VF = std::max( - TTI.getRegisterBitWidth(true) / + TTI.getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) + .getFixedSize() / Result.getElementType()->getPrimitiveSizeInBits().getFixedSize(), 1U); unsigned R = Result.getNumRows(); @@ -1179,10 +1182,11 @@ const unsigned M = LShape.NumColumns; auto *EltType = cast(MatMul->getType())->getElementType(); - const unsigned VF = - std::max(TTI.getRegisterBitWidth(true) / - EltType->getPrimitiveSizeInBits().getFixedSize(), - 1U); + const unsigned VF = std::max( + TTI.getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) + .getFixedSize() / + EltType->getPrimitiveSizeInBits().getFixedSize(), + 1U); // Cost model for tiling // diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -5699,7 +5699,9 @@ MinBWs = computeMinimumValueSizes(TheLoop->getBlocks(), *DB, &TTI); unsigned SmallestType, WidestType; std::tie(SmallestType, WidestType) = getSmallestAndWidestTypes(); - unsigned WidestRegister = TTI.getRegisterBitWidth(true); + unsigned WidestRegister = + TTI.getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) + .getFixedSize(); // Get the maximum safe dependence distance in bits computed by LAA. // It is computed by MaxVF * sizeOf(type) * 8, where type is taken from @@ -7661,8 +7663,10 @@ // If the user doesn't provide a vectorization factor, determine a // reasonable one. if (UserVF.isZero()) { - VF = ElementCount::getFixed( - determineVPlanVF(TTI->getRegisterBitWidth(true /* Vector*/), CM)); + VF = ElementCount::getFixed(determineVPlanVF( + TTI->getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) + .getFixedSize(), + CM)); LLVM_DEBUG(dbgs() << "LV: VPlan computed VF " << VF << ".\n"); // Make sure we have a VF > 1 for stress testing. diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -570,7 +570,9 @@ if (MaxVectorRegSizeOption.getNumOccurrences()) MaxVecRegSize = MaxVectorRegSizeOption; else - MaxVecRegSize = TTI->getRegisterBitWidth(true); + MaxVecRegSize = + TTI->getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) + .getFixedSize(); if (MinVectorRegSizeOption.getNumOccurrences()) MinVecRegSize = MinVectorRegSizeOption;