diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -412,7 +412,9 @@
   // Prevent assignment of base register to X0, which is inappropriate
   // for loads and stores alike.
   if (Addr.Base.Reg != 0)
-    MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
+    MRI.setRegClass(Addr.Base.Reg, Subtarget->isPPC64()
+                                       ? &PPC::G8RC_and_G8RC_NOX0RegClass
+                                       : &PPC::GPRC_and_GPRC_NOR0RegClass);
 
   return Addr.Base.Reg != 0;
 }
@@ -431,18 +433,24 @@
   // put the alloca address into a register, set the base type back to
   // register and continue. This should almost never happen.
   if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
-    unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
-            ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
+    unsigned ResultReg = createResultReg(
+        Subtarget->isPPC64() ? &PPC::G8RC_and_G8RC_NOX0RegClass
+                             : &PPC::GPRC_and_GPRC_NOR0RegClass);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+            TII.get(Subtarget->isPPC64() ? PPC::ADDI8 : PPC::ADDI), ResultReg)
+        .addFrameIndex(Addr.Base.FI)
+        .addImm(0);
     Addr.Base.Reg = ResultReg;
     Addr.BaseType = Address::RegBase;
   }
 
   if (!UseOffset) {
-    IntegerType *OffsetTy = Type::getInt64Ty(*Context);
+    IntegerType *OffsetTy = Subtarget->isPPC64() ? Type::getInt64Ty(*Context)
+                                                 : Type::getInt32Ty(*Context);
     const ConstantInt *Offset =
-      ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
-    IndexReg = PPCMaterializeInt(Offset, MVT::i64);
+        ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
+    IndexReg =
+        PPCMaterializeInt(Offset, Subtarget->isPPC64() ? MVT::i64 : MVT::i32);
     assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
   }
 }
@@ -1020,7 +1028,7 @@
                                      bool IsSigned) {
 
   // If necessary, extend 32-bit int to 64-bit.
-  if (SrcVT == MVT::i32) {
+  if (SrcVT == MVT::i32 && Subtarget->isPPC64()) {
     unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
     if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
       return 0;
@@ -1033,7 +1041,7 @@
   Addr.Base.FI = MFI.CreateStackObject(8, Align(8), false);
 
   // Store the value from the GPR.
-  if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
+  if (!PPCEmitStore(Subtarget->isPPC64() ? MVT::i64 : MVT::i32, SrcReg, Addr))
     return 0;
 
   // Load the integer value into an FPR.  The kind of load used depends
@@ -1115,7 +1123,7 @@
     return false;
 
   // Extend the input if necessary.
-  if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
+  if ((SrcVT == MVT::i8 || SrcVT == MVT::i16) && Subtarget->isPPC64()) {
     unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
     if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
       return false;
@@ -1298,7 +1306,9 @@
       break;
   }
 
-  unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
+  unsigned ResultReg = createResultReg(
+      RC ? RC
+         : (Subtarget->isPPC64() ? &PPC::G8RCRegClass : &PPC::GPRCRegClass));
   unsigned SrcReg1 = getRegForValue(I->getOperand(0));
   if (SrcReg1 == 0) return false;
 
@@ -1424,7 +1434,7 @@
   // Prepare to assign register arguments.  Every argument uses up a
   // GPR protocol register even if it's passed in a floating-point
   // register (unless we're using the fast calling convention).
-  unsigned NextGPR = PPC::X3;
+  unsigned NextGPR = Subtarget->isPPC64() ? PPC::X3 : PPC::R3;
   unsigned NextFPR = PPC::F1;
 
   // Process arguments.
@@ -1513,7 +1523,7 @@
     // Ints smaller than a register still arrive in a full 64-bit
     // register, so make sure we recognize this.
     if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
-      CopyVT = MVT::i64;
+      CopyVT = Subtarget->isPPC64() ? MVT::i64 : MVT::i32;
 
     unsigned SourcePhysReg = VA.getLocReg();
     unsigned ResultReg = 0;
@@ -1678,7 +1688,7 @@
   // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
   // into the call.
   PPCFuncInfo->setUsesTOCBasePtr();
-  MIB.addReg(PPC::X2, RegState::Implicit);
+  MIB.addReg(Subtarget->isPPC64() ? PPC::X2 : PPC::R2, RegState::Implicit);
 
   // Add a register mask with the call-preserved registers.  Proper
   // defs for return values will be added by setPhysRegsDeadExcept().
@@ -1710,7 +1720,12 @@
     // Analyze operands of the call, assigning locations to each operand.
     SmallVector<CCValAssign, 16> ValLocs;
     CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
-    CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
+    if (Subtarget->is64BitELFABI())
+      CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
+    else if (Subtarget->isAIXABI())
+      CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
+    else
+      llvm_unreachable("Unsupported PPC ABI in FastISel!");
     const Value *RV = Ret->getOperand(0);
 
     // FIXME: Only one output register for now.
@@ -1728,7 +1743,8 @@
       // extension rather than sign extension. Make sure we pass the return
       // value extension property to integer materialization.
       unsigned SrcReg =
-          PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() != CCValAssign::ZExt);
+          PPCMaterializeInt(CI, Subtarget->isPPC64() ? MVT::i64 : MVT::i32,
+                            VA.getLocInfo() != CCValAssign::ZExt);
 
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
             TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
@@ -2028,24 +2044,31 @@
   else
     Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD);
 
-  unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
+  unsigned TmpReg =
+      createResultReg(Subtarget->isPPC64() ? &PPC::G8RC_and_G8RC_NOX0RegClass
+                                           : &PPC::GPRC_and_GPRC_NOR0RegClass);
 
   PPCFuncInfo->setUsesTOCBasePtr();
   // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
   if (CModel == CodeModel::Small) {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
             TmpReg)
-      .addConstantPoolIndex(Idx).addReg(PPC::X2);
+        .addConstantPoolIndex(Idx)
+        .addReg(Subtarget->isPPC64() ? PPC::X2 : PPC::R2);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
       .addImm(0).addReg(TmpReg).addMemOperand(MMO);
   } else {
     // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA8(X2, Idx)).
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
-            TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
+            TmpReg)
+        .addReg(Subtarget->isPPC64() ? PPC::X2 : PPC::R2)
+        .addConstantPoolIndex(Idx);
     // But for large code model, we must generate a LDtocL followed
     // by the LF[SD].
     if (CModel == CodeModel::Large) {
-      unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
+      unsigned TmpReg2 = createResultReg(
+          Subtarget->isPPC64() ? &PPC::G8RC_and_G8RC_NOX0RegClass
+                               : &PPC::GPRC_and_GPRC_NOR0RegClass);
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
               TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
@@ -2068,8 +2091,14 @@
   if (Subtarget->isUsingPCRelativeCalls())
     return false;
 
+  // TODO: Fix support for 32-bit mode
+  if (!Subtarget->isPPC64())
+    return 0;
+
   assert(VT == MVT::i64 && "Non-address!");
-  const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
+  const TargetRegisterClass *RC = Subtarget->isPPC64()
+                                      ? &PPC::G8RC_and_G8RC_NOX0RegClass
+                                      : &PPC::GPRC_and_GPRC_NOR0RegClass;
   unsigned DestReg = createResultReg(RC);
 
   // Global values may be plain old object addresses, TLS object
@@ -2091,7 +2120,7 @@
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
             DestReg)
         .addGlobalAddress(GV)
-        .addReg(PPC::X2);
+        .addReg(Subtarget->isPPC64() ? PPC::X2 : PPC::R2);
   else {
     // If the address is an externally defined symbol, a symbol with common
     // or externally available linkage, a non-local function address, or a
@@ -2103,7 +2132,9 @@
     // Either way, start with the ADDIStocHA8:
     unsigned HighPartReg = createResultReg(RC);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
-            HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
+            HighPartReg)
+        .addReg(Subtarget->isPPC64() ? PPC::X2 : PPC::R2)
+        .addGlobalAddress(GV);
 
     if (Subtarget->isGVIndirectSymbol(GV)) {
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
@@ -2285,7 +2316,9 @@
     FuncInfo.StaticAllocaMap.find(AI);
 
   if (SI != FuncInfo.StaticAllocaMap.end()) {
-    unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
+    unsigned ResultReg = createResultReg(
+        Subtarget->isPPC64() ? &PPC::G8RC_and_G8RC_NOX0RegClass
+                             : &PPC::GPRC_and_GPRC_NOR0RegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
             ResultReg).addFrameIndex(SI->second).addImm(0);
     return ResultReg;
@@ -2475,7 +2508,7 @@
                                 const TargetLibraryInfo *LibInfo) {
     // Only available on 64-bit ELF for now.
     const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
-    if (Subtarget.is64BitELFABI())
+    if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI())
       return new PPCFastISel(FuncInfo, LibInfo);
     return nullptr;
   }
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll b/llvm/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
 
 %struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
 %struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
@@ -9,40 +10,40 @@
 
 define i32* @t1() nounwind {
 entry:
-; ELF64: t1
+; PPC64: t1
   %addr = alloca i32*, align 4
   store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]], [2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
-; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 124
+; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 124
   %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
 
 define i32* @t2() nounwind {
 entry:
-; ELF64: t2
+; PPC64: t2
   %addr = alloca i32*, align 4
   store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
-; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1148
+; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 1148
   %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
 
 define i32* @t3() nounwind {
 entry:
-; ELF64: t3
+; PPC64: t3
   %addr = alloca i32*, align 4
   store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
-; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 140
+; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 140
   %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
 
 define i32* @t4() nounwind {
 entry:
-; ELF64: t4
+; PPC64: t4
   %addr = alloca i32*, align 4
   store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]], [2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
-; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1284
+; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 1284
   %0 = load i32*, i32** %addr, align 4
   ret i32* %0
 }
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-binary.ll b/llvm/test/CodeGen/PowerPC/fast-isel-binary.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-binary.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-binary.ll
@@ -1,43 +1,44 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
 
 ; Test add with non-legal types
 
 define void @add_i8(i8 %a, i8 %b) nounwind {
 entry:
-; ELF64: add_i8
+; PPC64: add_i8
   %a.addr = alloca i8, align 4
   %0 = add i8 %a, %b
-; ELF64: add
+; PPC64: add
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @add_i8_imm(i8 %a) nounwind {
 entry:
-; ELF64: add_i8_imm
+; PPC64: add_i8_imm
   %a.addr = alloca i8, align 4
   %0 = add i8 %a, 22;
-; ELF64: addi
+; PPC64: addi
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @add_i16(i16 %a, i16 %b) nounwind {
 entry:
-; ELF64: add_i16
+; PPC64: add_i16
   %a.addr = alloca i16, align 4
   %0 = add i16 %a, %b
-; ELF64: add
+; PPC64: add
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
 
 define void @add_i16_imm(i16 %a, i16 %b) nounwind {
 entry:
-; ELF64: add_i16_imm
+; PPC64: add_i16_imm
   %a.addr = alloca i16, align 4
   %0 = add i16 %a, 243;
-; ELF64: addi
+; PPC64: addi
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
@@ -46,40 +47,40 @@
 
 define void @or_i8(i8 %a, i8 %b) nounwind {
 entry:
-; ELF64: or_i8
+; PPC64: or_i8
   %a.addr = alloca i8, align 4
   %0 = or i8 %a, %b
-; ELF64: or
+; PPC64: or
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @or_i8_imm(i8 %a) nounwind {
 entry:
-; ELF64: or_i8_imm
+; PPC64: or_i8_imm
   %a.addr = alloca i8, align 4
   %0 = or i8 %a, -13;
-; ELF64: ori
+; PPC64: ori
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @or_i16(i16 %a, i16 %b) nounwind {
 entry:
-; ELF64: or_i16
+; PPC64: or_i16
   %a.addr = alloca i16, align 4
   %0 = or i16 %a, %b
-; ELF64: or
+; PPC64: or
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
 
 define void @or_i16_imm(i16 %a) nounwind {
 entry:
-; ELF64: or_i16_imm
+; PPC64: or_i16_imm
   %a.addr = alloca i16, align 4
   %0 = or i16 %a, 273;
-; ELF64: ori
+; PPC64: ori
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
@@ -88,50 +89,50 @@
 
 define void @sub_i8(i8 %a, i8 %b) nounwind {
 entry:
-; ELF64: sub_i8
+; PPC64: sub_i8
   %a.addr = alloca i8, align 4
   %0 = sub i8 %a, %b
-; ELF64: sub
+; PPC64: sub
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @sub_i8_imm(i8 %a) nounwind {
 entry:
-; ELF64: sub_i8_imm
+; PPC64: sub_i8_imm
   %a.addr = alloca i8, align 4
   %0 = sub i8 %a, 22;
-; ELF64: addi
+; PPC64: addi
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @sub_i16(i16 %a, i16 %b) nounwind {
 entry:
-; ELF64: sub_i16
+; PPC64: sub_i16
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, %b
-; ELF64: sub
+; PPC64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
 
 define void @sub_i16_imm(i16 %a) nounwind {
 entry:
-; ELF64: sub_i16_imm
+; PPC64: sub_i16_imm
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, 247;
-; ELF64: addi
+; PPC64: addi
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
 
 define void @sub_i16_badimm(i16 %a) nounwind {
 entry:
-; ELF64: sub_i16_imm
+; PPC64: sub_i16_imm
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, -32768;
-; ELF64: sub
+; PPC64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-const.ll b/llvm/test/CodeGen/PowerPC/fast-isel-const.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-const.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-const.ll
@@ -1,27 +1,28 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
 
 define zeroext i1 @testi1(i8 %in) nounwind {
 entry:
   %c = icmp eq i8 %in, 5
   br i1 %c, label %true, label %false
 
-; ELF64-LABEL: @testi1
+; PPC64-LABEL: @testi1
 
 true:
   br label %end
 
-; ELF64-NOT: li {{[0-9]+}}, -1
-; ELF64: li {{[0-9]+}}, 1
+; PPC64-NOT: li {{[0-9]+}}, -1
+; PPC64: li {{[0-9]+}}, 1
 
 false:
   br label %end
 
-; ELF64: li {{[0-9]+}}, 0
+; PPC64: li {{[0-9]+}}, 0
 
 end:
   %r = phi i1 [ 0, %false], [ 1, %true ]
   ret i1 %r
 
-; ELF64: blr
+; PPC64: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-crash.ll b/llvm/test/CodeGen/PowerPC/fast-isel-crash.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-crash.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-crash.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7
 
 ; Ensure this doesn't crash.
 
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll b/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll
@@ -1,75 +1,76 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
 
 ; zext
 
 define i32 @zext_8_32(i8 %a) nounwind {
-; ELF64: zext_8_32
+; PPC64: zext_8_32
   %r = zext i8 %a to i32
-; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
+; PPC64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
   ret i32 %r
 }
 
 define i32 @zext_16_32(i16 %a) nounwind {
-; ELF64: zext_16_32
+; PPC64: zext_16_32
   %r = zext i16 %a to i32
-; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
+; PPC64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
   ret i32 %r
 }
 
 define i64 @zext_8_64(i8 %a) nounwind {
-; ELF64: zext_8_64
+; PPC64: zext_8_64
   %r = zext i8 %a to i64
-; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
+; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
   ret i64 %r
 }
 
 define i64 @zext_16_64(i16 %a) nounwind {
-; ELF64: zext_16_64
+; PPC64: zext_16_64
   %r = zext i16 %a to i64
-; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
+; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
   ret i64 %r
 }
 
 define i64 @zext_32_64(i32 %a) nounwind {
-; ELF64: zext_32_64
+; PPC64: zext_32_64
   %r = zext i32 %a to i64
-; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
   ret i64 %r
 }
 
 ; sext
 
 define i32 @sext_8_32(i8 %a) nounwind {
-; ELF64: sext_8_32
+; PPC64: sext_8_32
   %r = sext i8 %a to i32
-; ELF64: extsb
+; PPC64: extsb
   ret i32 %r
 }
 
 define i32 @sext_16_32(i16 %a) nounwind {
-; ELF64: sext_16_32
+; PPC64: sext_16_32
   %r = sext i16 %a to i32
-; ELF64: extsh
+; PPC64: extsh
   ret i32 %r
 }
 
 define i64 @sext_8_64(i8 %a) nounwind {
-; ELF64: sext_8_64
+; PPC64: sext_8_64
   %r = sext i8 %a to i64
-; ELF64: extsb
+; PPC64: extsb
   ret i64 %r
 }
 
 define i64 @sext_16_64(i16 %a) nounwind {
-; ELF64: sext_16_64
+; PPC64: sext_16_64
   %r = sext i16 %a to i64
-; ELF64: extsh
+; PPC64: extsh
   ret i64 %r
 }
 
 define i64 @sext_32_64(i32 %a) nounwind {
-; ELF64: sext_32_64
+; PPC64: sext_32_64
   %r = sext i32 %a to i64
-; ELF64: extsw
+; PPC64: extsw
   ret i64 %r
 }
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-fold.ll b/llvm/test/CodeGen/PowerPC/fast-isel-fold.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-fold.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-fold.ll
@@ -1,36 +1,37 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
 
 @a = global i8 1, align 1
 @b = global i16 2, align 2
 @c = global i32 4, align 4
 
 define void @t1() nounwind {
-; ELF64: t1
+; PPC64: t1
   %1 = load i8, i8* @a, align 1
   call void @foo1(i8 zeroext %1)
-; ELF64: lbz
-; ELF64-NOT: rldicl
-; ELF64-NOT: rlwinm
+; PPC64: lbz
+; PPC64-NOT: rldicl
+; PPC64-NOT: rlwinm
   ret void
 }
 
 define void @t2() nounwind {
-; ELF64: t2
+; PPC64: t2
   %1 = load i16, i16* @b, align 2
   call void @foo2(i16 zeroext %1)
-; ELF64: lhz
-; ELF64-NOT: rldicl
-; ELF64-NOT: rlwinm
+; PPC64: lhz
+; PPC64-NOT: rldicl
+; PPC64-NOT: rlwinm
   ret void
 }
 
 define void @t2a() nounwind {
-; ELF64: t2a
+; PPC64: t2a
   %1 = load i32, i32* @c, align 4
   call void @foo3(i32 zeroext %1)
-; ELF64: lwz
-; ELF64-NOT: rldicl
-; ELF64-NOT: rlwinm
+; PPC64: lwz
+; PPC64-NOT: rldicl
+; PPC64-NOT: rlwinm
   ret void
 }
 
@@ -39,91 +40,91 @@
 declare void @foo3(i32 zeroext)
 
 define i32 @t3() nounwind {
-; ELF64: t3
+; PPC64: t3
   %1 = load i8, i8* @a, align 1
   %2 = zext i8 %1 to i32
-; ELF64: lbz
-; ELF64-NOT: rlwinm
+; PPC64: lbz
+; PPC64-NOT: rlwinm
   ret i32 %2
 }
 
 define i32 @t4() nounwind {
-; ELF64: t4
+; PPC64: t4
   %1 = load i16, i16* @b, align 2
   %2 = zext i16 %1 to i32
-; ELF64: lhz
-; ELF64-NOT: rlwinm
+; PPC64: lhz
+; PPC64-NOT: rlwinm
   ret i32 %2
 }
 
 define i32 @t5() nounwind {
-; ELF64: t5
+; PPC64: t5
   %1 = load i16, i16* @b, align 2
   %2 = sext i16 %1 to i32
-; ELF64: lha
-; ELF64-NOT: rlwinm
+; PPC64: lha
+; PPC64-NOT: rlwinm
   ret i32 %2
 }
 
 define i32 @t6() nounwind {
-; ELF64: t6
+; PPC64: t6
   %1 = load i8, i8* @a, align 2
   %2 = sext i8 %1 to i32
-; ELF64: lbz
-; ELF64-NOT: rlwinm
+; PPC64: lbz
+; PPC64-NOT: rlwinm
   ret i32 %2
 }
 
 define i64 @t7() nounwind {
-; ELF64: t7
+; PPC64: t7
   %1 = load i8, i8* @a, align 1
   %2 = zext i8 %1 to i64
-; ELF64: lbz
-; ELF64-NOT: rldicl
+; PPC64: lbz
+; PPC64-NOT: rldicl
   ret i64 %2
 }
 
 define i64 @t8() nounwind {
-; ELF64: t8
+; PPC64: t8
   %1 = load i16, i16* @b, align 2
   %2 = zext i16 %1 to i64
-; ELF64: lhz
-; ELF64-NOT: rldicl
+; PPC64: lhz
+; PPC64-NOT: rldicl
   ret i64 %2
 }
 
 define i64 @t9() nounwind {
-; ELF64: t9
+; PPC64: t9
   %1 = load i16, i16* @b, align 2
   %2 = sext i16 %1 to i64
-; ELF64: lha
-; ELF64-NOT: extsh
+; PPC64: lha
+; PPC64-NOT: extsh
   ret i64 %2
 }
 
 define i64 @t10() nounwind {
-; ELF64: t10
+; PPC64: t10
   %1 = load i8, i8* @a, align 2
   %2 = sext i8 %1 to i64
-; ELF64: lbz
-; ELF64: extsb
+; PPC64: lbz
+; PPC64: extsb
   ret i64 %2
 }
 
 define i64 @t11() nounwind {
-; ELF64: t11
+; PPC64: t11
   %1 = load i32, i32* @c, align 4
   %2 = zext i32 %1 to i64
-; ELF64: lwz
-; ELF64-NOT: rldicl
+; PPC64: lwz
+; PPC64-NOT: rldicl
   ret i64 %2
 }
 
 define i64 @t12() nounwind {
-; ELF64: t12
+; PPC64: t12
   %1 = load i32, i32* @c, align 4
   %2 = sext i32 %1 to i64
-; ELF64: lwa
-; ELF64-NOT: extsw
+; PPC64: lwa
+; PPC64-NOT: extsw
   ret i64 %2
 }
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-i64offset.ll b/llvm/test/CodeGen/PowerPC/fast-isel-i64offset.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-i64offset.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-i64offset.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -fast-isel -O0 < %s | FileCheck %s
 
 ; Verify that pointer offsets larger than 32 bits work correctly.
 
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-indirectbr.ll b/llvm/test/CodeGen/PowerPC/fast-isel-indirectbr.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-indirectbr.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-indirectbr.ll
@@ -1,8 +1,9 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
 
 define void @t1(i8* %x) nounwind {
 entry:
-; ELF64: t1
+; PPC64: t1
   br label %L0
 
 L0:
@@ -10,6 +11,6 @@
 
 L1:
   indirectbr i8* %x, [ label %L0, label %L1 ]
-; ELF64: mtctr 3
-; ELF64: bctr
+; PPC64: mtctr 3
+; PPC64: bctr
 }
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-shifter.ll b/llvm/test/CodeGen/PowerPC/fast-isel-shifter.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-shifter.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-shifter.ll
@@ -1,49 +1,50 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
 
 define i32 @shl() nounwind {
 entry:
-; ELF64: shl
-; ELF64: slw
+; PPC64: shl
+; PPC64: slw
   %shl = shl i32 -1, 2
   ret i32 %shl
 }
 
 define i32 @shl_reg(i32 %src1, i32 %src2) nounwind {
 entry:
-; ELF64: shl_reg
-; ELF64: slw
+; PPC64: shl_reg
+; PPC64: slw
   %shl = shl i32 %src1, %src2
   ret i32 %shl
 }
 
 define i32 @lshr() nounwind {
 entry:
-; ELF64: lshr
-; ELF64: srw
+; PPC64: lshr
+; PPC64: srw
   %lshr = lshr i32 -1, 2
   ret i32 %lshr
 }
 
 define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind {
 entry:
-; ELF64: lshr_reg
-; ELF64: srw
+; PPC64: lshr_reg
+; PPC64: srw
   %lshr = lshr i32 %src1, %src2
   ret i32 %lshr
 }
 
 define i32 @ashr() nounwind {
 entry:
-; ELF64: ashr
-; ELF64: srawi
+; PPC64: ashr
+; PPC64: srawi
   %ashr = ashr i32 -1, 2
   ret i32 %ashr
 }
 
 define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind {
 entry:
-; ELF64: ashr_reg
-; ELF64: sraw
+; PPC64: ashr_reg
+; PPC64: sraw
   %ashr = ashr i32 %src1, %src2
   ret i32 %ashr
 }