Index: llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir @@ -0,0 +1,46 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -o - %s \ +# RUN: -start-before=prologepilog | FileCheck %s +--- | + define void @foo() #0 + ; CHECK-LABEL: foo: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: addi sp, sp, -16 + ; CHECK-NEXT: sw s9, 12(sp) # 4-byte Folded Spill + ; CHECK-NEXT: csrr a1, vlenb + ; CHECK-NEXT: slli a1, a1, 1 + ; CHECK-NEXT: sub sp, sp, a1 + ; CHECK-NEXT: sw a0, 8(sp) # 4-byte Folded Spill + ; CHECK-NEXT: vs2r.v v30, (sp) # Unknown-size Folded Spill + ; CHECK-NEXT: csrr a0, vlenb + ; CHECK-NEXT: slli a0, a0, 1 + ; CHECK-NEXT: add sp, sp, a0 + ; CHECK-NEXT: lw s9, 12(sp) # 4-byte Folded Reload + ; CHECK-NEXT: addi sp, sp, 16 + ; CHECK-NEXT: ret + { + entry: + ret void + } + + attributes #0 = { nounwind } +... +--- +name: foo +alignment: 2 +frameInfo: + maxAlignment: 8 +stack: + - { id: 0, type: spill-slot, size: 4, alignment: 4 } + - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector } +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $v30m2 + + $x25 = COPY $x10 + SW renamable $x25, %stack.0, 0 :: (store 4 into %stack.0) + PseudoVSPILL_M2 renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8) + PseudoRET + +... Index: llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -o - %s \ +# RUN: -start-before=prologepilog | FileCheck %s +--- | + define void @foo() #0 + ; CHECK-LABEL: foo: + ; CHECK: # %bb.0: # %entry + ; CHECK-NEXT: addi sp, sp, -32 + ; CHECK-NEXT: sd s9, 24(sp) # 8-byte Folded Spill + ; CHECK-NEXT: csrr a1, vlenb + ; CHECK-NEXT: slli a1, a1, 1 + ; CHECK-NEXT: sub sp, sp, a1 + ; CHECK-NEXT: sd a0, 16(sp) # 8-byte Folded Spill + ; CHECK-NEXT: addi a0, sp, 16 + ; CHECK-NEXT: vs2r.v v30, (a0) # Unknown-size Folded Spill + ; CHECK-NEXT: csrr a0, vlenb + ; CHECK-NEXT: slli a0, a0, 1 + ; CHECK-NEXT: add sp, sp, a0 + ; CHECK-NEXT: ld s9, 24(sp) # 8-byte Folded Reload + ; CHECK-NEXT: addi sp, sp, 32 + ; CHECK-NEXT: ret + { + entry: + ret void + } + + attributes #0 = { nounwind } +... +--- +name: foo +alignment: 2 +tracksRegLiveness: true +frameInfo: + maxAlignment: 8 +stack: + - { id: 0, type: spill-slot, size: 8, alignment: 8 } + - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector } +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $v30m2 + + $x25 = COPY $x10 + SD renamable $x25, %stack.0, 0 :: (store 8 into %stack.0) + PseudoVSPILL_M2 renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8) + PseudoRET + +...