Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -13147,6 +13147,13 @@
   SDValue RHS = Op->getOperand(1);
   SetCCInfoAndKind InfoAndKind;
 
+  // If both operands are a SET_CC, then we don't want to perform this
+  // folding and create another csel as this results in more instructions
+  // (and higher register usage).
+  if (isSetCCOrZExtSetCC(LHS, InfoAndKind) &&
+      isSetCCOrZExtSetCC(RHS, InfoAndKind))
+    return SDValue();
+
   // If neither operand is a SET_CC, give up.
   if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
     std::swap(LHS, RHS);
Index: llvm/test/CodeGen/AArch64/arm64-csel.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-csel.ll
+++ llvm/test/CodeGen/AArch64/arm64-csel.ll
@@ -274,12 +274,11 @@
 ; CHECK-LABEL: foo24:
 ; CHECK:       ldrb    w[[W8:[0-9]+]], [x0]
 ; CHECK-NEXT:  ldrb    w[[W9:[0-9]+]], [x1]
-; CHECK-NEXT:  mov     w[[W10:[0-9]+]], #2
 ; CHECK-NEXT:  cmp     w[[W8]], #3
 ; CHECK-NEXT:  cset    w[[W8]], hi
-; CHECK-NEXT:  csinc   w[[W10]], w[[W10]], wzr, hi
 ; CHECK-NEXT:  cmp     w[[W9]], #33
-; CHECK-NEXT:  csel    w0, w[[W8]], w[[W10]], ls
+; CHECK-NEXT:  cset    w[[W9]], hi
+; CHECK-NEXT:  add     w0, w[[W9]], w[[W8]]
 ; CHECK-NEXT:  ret
 entry:
   %0 = load i8, i8* %A, align 1