[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.

[craig.topper]

Summary

The default promotion uses zero extends that become shifts. We
cam use sign extend instead which is better for RISCV.

I've used two different implementations based on whether we
have minu/maxu instructions.

[luismarques]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3529

Nit: British spelling :)

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3529

Yeah I copied and pasted it from one of the other cases. Figured it was best to be consistent.

[luismarques]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3529

Yeah I copied and pasted it from one of the other cases. Figured it was best to be consistent.

Oh, right. I see it's all @asb's original fault :)
Good call. Keep it consistent, and no point in polluting the git blame history changing the others trivially.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.is64Bit()) {
     setOperationAction(ISD::ADD, MVT::i32, Custom);
     setOperationAction(ISD::SUB, MVT::i32, Custom);
     setOperationAction(ISD::SHL, MVT::i32, Custom);
     setOperationAction(ISD::SRA, MVT::i32, Custom);
     setOperationAction(ISD::SRL, MVT::i32, Custom);
 
     setOperationAction(ISD::UADDO, MVT::i32, Custom);
     setOperationAction(ISD::USUBO, MVT::i32, Custom);
+    setOperationAction(ISD::UADDSAT, MVT::i32, Custom);
+    setOperationAction(ISD::USUBSAT, MVT::i32, Custom);
   }
 
   if (!Subtarget.hasStdExtM()) {
     setOperationAction(ISD::MUL, XLenVT, Expand);
     setOperationAction(ISD::MULHS, XLenVT, Expand);
     setOperationAction(ISD::MULHU, XLenVT, Expand);
     setOperationAction(ISD::SDIV, XLenVT, Expand);
     setOperationAction(ISD::UDIV, XLenVT, Expand);
case ISD::USUBO: {
     LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, N->getOperand(0));
     SDValue Overflow = DAG.getSetCC(DL, N->getValueType(1), Res, LHS,
                                     IsAdd ? ISD::SETULT : ISD::SETUGT);
 
     Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
     Results.push_back(Overflow);
     return;
   }
+  case ISD::UADDSAT:
+  case ISD::USUBSAT: {
+    assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+           "Unexpected custom legalisation");
+    SDLoc DL(N);
+    if (Subtarget.hasStdExtZbb()) {
+      // With Zbb we can sign extend and let LegalizeDAG use minu/maxu. Using
+      // sign extend allows overflow of the lower 32 bits to be detected on
+      // the promoted size.
+      SDValue LHS =
+          DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, N->getOperand(0));
+      SDValue RHS =
+          DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, N->getOperand(1));
+      SDValue Res = DAG.getNode(N->getOpcode(), DL, MVT::i64, LHS, RHS);
+      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+      return;
+    }
+
+    // Without Zbb, expand to UADDO/USUBO+select which will trigger our custom
+    // promotion for UADDO/USUBO.
+    Results.push_back(expandAddSubSat(N, DAG));
+    return;
+  }
   case ISD::BITCAST: {
     assert(((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
              Subtarget.hasStdExtF()) ||
             (N->getValueType(0) == MVT::i16 && Subtarget.hasStdExtZfh())) &&
            "Unexpected custom legalisation");
     SDValue Op0 = N->getOperand(0);
     if (N->getValueType(0) == MVT::i16 && Subtarget.hasStdExtZfh()) {
       if (Op0.getValueType() != MVT::f16)

llvm/test/CodeGen/RISCV/uadd_sat.ll

 ; RV32I-NEXT:    bltu a1, a2, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    add a0, a0, a1
-; RV64I-NEXT:    addi a1, zero, 1
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    addi a1, a1, -1
-; RV64I-NEXT:    bltu a0, a1, .LBB0_2
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    addw a1, a0, a1
+; RV64I-NEXT:    addi a0, zero, -1
+; RV64I-NEXT:    bltu a1, a2, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB0_2:
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    not a2, a1
 ; RV32IZbb-NEXT:    minu a0, a0, a2
 ; RV32IZbb-NEXT:    add a0, a0, a1
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func:
 ; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    slli a1, a1, 32
-; RV64IZbb-NEXT:    srli a1, a1, 32
-; RV64IZbb-NEXT:    slli a0, a0, 32
-; RV64IZbb-NEXT:    srli a0, a0, 32
-; RV64IZbb-NEXT:    add a0, a0, a1
-; RV64IZbb-NEXT:    addi a1, zero, 1
-; RV64IZbb-NEXT:    slli a1, a1, 32
-; RV64IZbb-NEXT:    addi a1, a1, -1
-; RV64IZbb-NEXT:    minu a0, a0, a1
-; RV64IZbb-NEXT:    sext.w a0, a0
+; RV64IZbb-NEXT:    not a2, a1
+; RV64IZbb-NEXT:    minu a0, a0, a2
+; RV64IZbb-NEXT:    addw a0, a0, a1
 ; RV64IZbb-NEXT:    ret
   %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: func2:
 ; RV32I:       # %bb.0:

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

 ; RV32I-NEXT:    bltu a1, a3, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    mul a1, a1, a2
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    add a0, a0, a1
-; RV64I-NEXT:    addi a1, zero, 1
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    addi a1, a1, -1
-; RV64I-NEXT:    bltu a0, a1, .LBB0_2
+; RV64I-NEXT:    addw a1, a0, a1
+; RV64I-NEXT:    sext.w a2, a0
+; RV64I-NEXT:    addi a0, zero, -1
+; RV64I-NEXT:    bltu a1, a2, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB0_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func32:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mul a1, a1, a2
 ; RV32IZbb-NEXT:    not a2, a1
 ; RV32IZbb-NEXT:    minu a0, a0, a2
 ; RV32IZbb-NEXT:    add a0, a0, a1
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func32:
 ; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    slli a0, a0, 32
-; RV64IZbb-NEXT:    srli a0, a0, 32
-; RV64IZbb-NEXT:    mul a1, a1, a2
-; RV64IZbb-NEXT:    slli a1, a1, 32
-; RV64IZbb-NEXT:    srli a1, a1, 32
+; RV64IZbb-NEXT:    mulw a1, a1, a2
+; RV64IZbb-NEXT:    not a2, a1
+; RV64IZbb-NEXT:    sext.w a0, a0
+; RV64IZbb-NEXT:    minu a0, a0, a2
 ; RV64IZbb-NEXT:    add a0, a0, a1
-; RV64IZbb-NEXT:    addi a1, zero, 1
-; RV64IZbb-NEXT:    slli a1, a1, 32
-; RV64IZbb-NEXT:    addi a1, a1, -1
-; RV64IZbb-NEXT:    minu a0, a0, a1
 ; RV64IZbb-NEXT:    ret
   %a = mul i32 %y, %z
   %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)
   ret i32 %tmp
 }
 
 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32I-LABEL: func64:

llvm/test/CodeGen/RISCV/usub_sat.ll

 ; RV32I-NEXT:    bltu a2, a1, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a2, a0, 32
-; RV64I-NEXT:    sub a0, a2, a1
-; RV64I-NEXT:    mv a1, zero
-; RV64I-NEXT:    bltu a2, a0, .LBB0_2
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    subw a1, a0, a1
+; RV64I-NEXT:    mv a0, zero
+; RV64I-NEXT:    bltu a2, a1, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB0_2:
-; RV64I-NEXT:    sext.w a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    maxu a0, a0, a1
 ; RV32IZbb-NEXT:    sub a0, a0, a1
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func:
 ; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    slli a2, a1, 32
-; RV64IZbb-NEXT:    srli a2, a2, 32
-; RV64IZbb-NEXT:    slli a0, a0, 32
-; RV64IZbb-NEXT:    srli a0, a0, 32
-; RV64IZbb-NEXT:    maxu a0, a0, a2
+; RV64IZbb-NEXT:    maxu a0, a0, a1
 ; RV64IZbb-NEXT:    subw a0, a0, a1
 ; RV64IZbb-NEXT:    ret
   %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: func2:

llvm/test/CodeGen/RISCV/usub_sat_plus.ll

 ; RV32I-NEXT:    bltu a3, a1, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a3, a0, 32
-; RV64I-NEXT:    mul a0, a1, a2
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    sub a1, a3, a0
+; RV64I-NEXT:    mul a1, a1, a2
+; RV64I-NEXT:    subw a1, a0, a1
+; RV64I-NEXT:    sext.w a2, a0
 ; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bltu a3, a1, .LBB0_2
+; RV64I-NEXT:    bltu a2, a1, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB0_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func32:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mul a1, a1, a2
 ; RV32IZbb-NEXT:    maxu a0, a0, a1
 ; RV32IZbb-NEXT:    sub a0, a0, a1
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func32:
 ; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    slli a0, a0, 32
-; RV64IZbb-NEXT:    srli a0, a0, 32
-; RV64IZbb-NEXT:    mul a1, a1, a2
-; RV64IZbb-NEXT:    slli a1, a1, 32
-; RV64IZbb-NEXT:    srli a1, a1, 32
+; RV64IZbb-NEXT:    mulw a1, a1, a2
+; RV64IZbb-NEXT:    sext.w a0, a0
 ; RV64IZbb-NEXT:    maxu a0, a0, a1
 ; RV64IZbb-NEXT:    sub a0, a0, a1
 ; RV64IZbb-NEXT:    ret
   %a = mul i32 %y, %z
   %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)
   ret i32 %tmp
 }