diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -36,8 +36,10 @@
 #define GET_SUBTARGETINFO_CTOR
 #include "PPCGenSubtargetInfo.inc"
 
-static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
-cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
+static cl::opt<bool>
+    UseSubRegLiveness("ppc-track-subreg-liveness",
+                      cl::desc("Enable subregister liveness tracking for PPC"),
+                      cl::Hidden);
 
 static cl::opt<bool>
     EnableMachinePipeliner("ppc-enable-pipeliner",
@@ -170,7 +172,7 @@
     SecurePlt = true;
 
   if (HasSPE && IsPPC64)
-    report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
+    report_fatal_error("SPE is only supported for 32-bit targets.\n", false);
   if (HasSPE && (HasAltivec || HasVSX || HasFPU))
     report_fatal_error(
         "SPE and traditional floating point cannot both be enabled.\n", false);
@@ -196,14 +198,15 @@
 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
 
-PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
+PPCGenSubtargetInfo::AntiDepBreakMode
+PPCSubtarget::getAntiDepBreakMode() const {
   return TargetSubtargetInfo::ANTIDEP_ALL;
 }
 
 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
   CriticalPathRCs.clear();
-  CriticalPathRCs.push_back(isPPC64() ?
-                            &PPC::G8RCRegClass : &PPC::GPRCRegClass);
+  CriticalPathRCs.push_back(isPPC64() ? &PPC::G8RCRegClass
+                                      : &PPC::GPRCRegClass);
 }
 
 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
@@ -219,13 +222,9 @@
   Policy.ShouldTrackPressure = true;
 }
 
-bool PPCSubtarget::useAA() const {
-  return true;
-}
+bool PPCSubtarget::useAA() const { return true; }
 
-bool PPCSubtarget::enableSubRegLiveness() const {
-  return UseSubRegLiveness;
-}
+bool PPCSubtarget::enableSubRegLiveness() const { return UseSubRegLiveness; }
 
 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
   // Large code model always uses the TOC even for local symbols.
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -27,6 +27,7 @@
   enum PPCABI { PPC_ABI_UNKNOWN, PPC_ABI_ELFv1, PPC_ABI_ELFv2 };
   enum Endian { NOT_DETECTED, LITTLE, BIG };
   Endian Endianness = Endian::NOT_DETECTED;
+
 private:
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   PPCABI TargetABI;
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -49,54 +49,52 @@
 
 using namespace llvm;
 
+static cl::opt<bool> EnableBranchCoalescing(
+    "enable-ppc-branch-coalesce", cl::Hidden,
+    cl::desc("enable coalescing of duplicate branches for PPC"));
+static cl::opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
+                                     cl::desc("Disable CTR loops for PPC"));
 
 static cl::opt<bool>
-    EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
-                           cl::desc("enable coalescing of duplicate branches for PPC"));
-static cl::
-opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
-                        cl::desc("Disable CTR loops for PPC"));
-
-static cl::
-opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
-                            cl::desc("Disable PPC loop instr form prep"));
+    DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
+                         cl::desc("Disable PPC loop instr form prep"));
 
 static cl::opt<bool>
-VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
-  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
-
-static cl::
-opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
-                                cl::desc("Disable VSX Swap Removal for PPC"));
+    VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden,
+                      cl::desc("Schedule VSX FMA instruction mutation early"));
 
-static cl::
-opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
-                            cl::desc("Disable machine peepholes for PPC"));
+static cl::opt<bool>
+    DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
+                          cl::desc("Disable VSX Swap Removal for PPC"));
 
 static cl::opt<bool>
-EnableGEPOpt("ppc-gep-opt", cl::Hidden,
-             cl::desc("Enable optimizations on complex GEPs"),
-             cl::init(true));
+    DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
+                      cl::desc("Disable machine peepholes for PPC"));
 
 static cl::opt<bool>
-EnablePrefetch("enable-ppc-prefetching",
-                  cl::desc("enable software prefetching on PPC"),
-                  cl::init(false), cl::Hidden);
+    EnableGEPOpt("ppc-gep-opt", cl::Hidden,
+                 cl::desc("Enable optimizations on complex GEPs"),
+                 cl::init(true));
 
 static cl::opt<bool>
-EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
-                      cl::desc("Add extra TOC register dependencies"),
-                      cl::init(true), cl::Hidden);
+    EnablePrefetch("enable-ppc-prefetching",
+                   cl::desc("enable software prefetching on PPC"),
+                   cl::init(false), cl::Hidden);
 
 static cl::opt<bool>
-EnableMachineCombinerPass("ppc-machine-combiner",
-                          cl::desc("Enable the machine combiner pass"),
+    EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
+                          cl::desc("Add extra TOC register dependencies"),
                           cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
-  ReduceCRLogical("ppc-reduce-cr-logicals",
-                  cl::desc("Expand eligible cr-logical binary ops to branches"),
-                  cl::init(true), cl::Hidden);
+    EnableMachineCombinerPass("ppc-machine-combiner",
+                              cl::desc("Enable the machine combiner pass"),
+                              cl::init(true), cl::Hidden);
+
+static cl::opt<bool> ReduceCRLogical(
+    "ppc-reduce-cr-logicals",
+    cl::desc("Expand eligible cr-logical binary ops to branches"),
+    cl::init(true), cl::Hidden);
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
   // Register the targets
   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
@@ -127,17 +125,15 @@
 }
 
 /// Return the datalayout string of a subtarget.
-static std::string getDataLayoutString(const Triple &T,
-                                       PPCTargetMachine *TM) {
+static std::string getDataLayoutString(const Triple &T, PPCTargetMachine *TM) {
   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
   std::string Ret;
 
   // Most PPC* platforms are big endian, PPC(64)LE is little endian.
-  if (T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle){
+  if (T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle) {
     Ret = "e";
     TM->Endianness = TM->Endian::LITTLE;
-  }
-  else{
+  } else {
     Ret = "E";
     TM->Endianness = TM->Endian::BIG;
   }
@@ -275,13 +271,12 @@
   return CodeModel::Medium;
 }
 
-
 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
   ScheduleDAGMILive *DAG =
-    new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
-                          std::make_unique<PPCPreRASchedStrategy>(C) :
-                          std::make_unique<GenericScheduler>(C));
+      new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy()
+                                   ? std::make_unique<PPCPreRASchedStrategy>(C)
+                                   : std::make_unique<GenericScheduler>(C));
   // add DAG Mutations here.
   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
   if (ST.hasStoreFusion())
@@ -292,13 +287,15 @@
   return DAG;
 }
 
-static ScheduleDAGInstrs *createPPCPostMachineScheduler(
-  MachineSchedContext *C) {
+static ScheduleDAGInstrs *
+createPPCPostMachineScheduler(MachineSchedContext *C) {
   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
   ScheduleDAGMI *DAG =
-    new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
-                      std::make_unique<PPCPostRASchedStrategy>(C) :
-                      std::make_unique<PostGenericScheduler>(C), true);
+      new ScheduleDAGMI(C,
+                        ST.usePPCPostRASchedStrategy()
+                            ? std::make_unique<PPCPostRASchedStrategy>(C)
+                            : std::make_unique<PostGenericScheduler>(C),
+                        true);
   // add DAG Mutations here.
   if (ST.hasStoreFusion())
     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
@@ -379,7 +376,7 @@
 class PPCPassConfig : public TargetPassConfig {
 public:
   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
-    : TargetPassConfig(TM, PM) {
+      : TargetPassConfig(TM, PM) {
     // At any optimization level above -O0 we use the Machine Scheduler and not
     // the default Post RA List Scheduler.
     if (TM.getOptLevel() != CodeGenOpt::None)
@@ -550,14 +547,13 @@
 }
 
 static MachineSchedRegistry
-PPCPreRASchedRegistry("ppc-prera",
-                      "Run PowerPC PreRA specific scheduler",
-                      createPPCMachineScheduler);
+    PPCPreRASchedRegistry("ppc-prera", "Run PowerPC PreRA specific scheduler",
+                          createPPCMachineScheduler);
 
 static MachineSchedRegistry
-PPCPostRASchedRegistry("ppc-postra",
-                       "Run PowerPC PostRA specific scheduler",
-                       createPPCPostMachineScheduler);
+    PPCPostRASchedRegistry("ppc-postra",
+                           "Run PowerPC PostRA specific scheduler",
+                           createPPCPostMachineScheduler);
 
 // Global ISEL
 bool PPCPassConfig::addIRTranslator() {