Index: llvm/lib/Target/AMDGPU/SOPInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -147,7 +147,7 @@
 }
 
 // 64-bit input, no output
-class SOP1_1 <string opName, RegisterClass rc = SReg_64, list<dag> pattern=[]> : SOP1_Pseudo <
+class SOP1_1 <string opName, RegisterOperand rc = SSrc_b64, list<dag> pattern=[]> : SOP1_Pseudo <
   opName, (outs), (ins rc:$src0), "$src0", pattern> {
   let has_sdst = 0;
 }
@@ -254,7 +254,8 @@
 
 let isReturn = 1 in {
 // Define variant marked as return rather than branch.
-def S_SETPC_B64_return : SOP1_1<"", CCR_SGPR_64, [(AMDGPUret_flag i64:$src0)]>;
+def S_SETPC_B64_return : SOP1_1<"", RegisterOperand<CCR_SGPR_64>,
+  [(AMDGPUret_flag i64:$src0)]>;
 }
 } // End isTerminator = 1, isBarrier = 1
 
Index: llvm/test/MC/AMDGPU/sop1.s
===================================================================
--- llvm/test/MC/AMDGPU/sop1.s
+++ llvm/test/MC/AMDGPU/sop1.s
@@ -218,6 +218,11 @@
 // GFX89: s_setpc_b64 s[4:5] ; encoding: [0x04,0x1d,0x80,0xbe]
 // GFX10: s_setpc_b64 s[4:5] ; encoding: [0x04,0x20,0x80,0xbe]
 
+s_setpc_b64 0
+// SICI: s_setpc_b64 0 ; encoding: [0x80,0x20,0x80,0xbe]
+// GFX89: s_setpc_b64 0 ; encoding: [0x80,0x1d,0x80,0xbe]
+// GFX10: s_setpc_b64 0 ; encoding: [0x80,0x20,0x80,0xbe]
+
 s_swappc_b64 s[2:3], s[4:5]
 // SICI: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x21,0x82,0xbe]
 // GFX89: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1e,0x82,0xbe]