diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -985,6 +985,7 @@
   SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
                                               SelectionDAG &DAG) const;
+  SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
                         SmallVectorImpl<SDNode *> &Created) const override;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1389,6 +1389,7 @@
   setOperationAction(ISD::CTLZ, VT, Custom);
   setOperationAction(ISD::CTPOP, VT, Custom);
   setOperationAction(ISD::CTTZ, VT, Custom);
+  setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
   setOperationAction(ISD::FADD, VT, Custom);
   setOperationAction(ISD::FCEIL, VT, Custom);
   setOperationAction(ISD::FDIV, VT, Custom);
@@ -9956,8 +9957,12 @@
                                                SelectionDAG &DAG) const {
   assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
 
+  SDValue Op0 = Op.getOperand(0);
+  EVT VT = Op0.getValueType();
+  if (useSVEForFixedLengthVectorVT(VT))
+    return LowerFixedLengthExtractVectorElt(Op, DAG);
+
   // Check for non-constant or out of range lane.
-  EVT VT = Op.getOperand(0).getValueType();
   ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
   if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
     return SDValue();
@@ -17113,6 +17118,19 @@
   return convertFromScalableVector(DAG, VT, Val);
 }
 
+SDValue AArch64TargetLowering::LowerFixedLengthExtractVectorElt(
+    SDValue Op, SelectionDAG &DAG) const {
+  EVT VT = Op.getValueType();
+  EVT InVT = Op.getOperand(0).getValueType();
+  assert(InVT.isFixedLengthVector() && "Expected fixed length vector type!");
+
+  SDLoc DL(Op);
+  EVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT);
+  SDValue Op0 = convertToScalableVector(DAG, ContainerVT, Op->getOperand(0));
+
+  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op0, Op.getOperand(1));
+}
+
 // Convert vector operation 'Op' to an equivalent predicated operation whereby
 // the original operation's type is used to construct a suitable predicate.
 // NOTE: The results for inactive lanes are undefined.
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
@@ -0,0 +1,189 @@
+; RUN: llc -aarch64-sve-vector-bits-min=128  -asm-verbose=0 < %s | FileCheck %s -check-prefix=NO_SVE
+; RUN: llc -aarch64-sve-vector-bits-min=256  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
+; RUN: llc -aarch64-sve-vector-bits-min=384  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
+; RUN: llc -aarch64-sve-vector-bits-min=512  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512
+; RUN: llc -aarch64-sve-vector-bits-min=640  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512
+; RUN: llc -aarch64-sve-vector-bits-min=768  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512
+; RUN: llc -aarch64-sve-vector-bits-min=896  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512
+; RUN: llc -aarch64-sve-vector-bits-min=1024 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1152 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1280 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1408 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1536 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1664 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1792 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1920 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=2048 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; Don't use SVE when its registers are no bigger than NEON.
+; NO_SVE-NOT: ptrue
+
+;
+; extractelement
+;
+
+; Don't use SVE for 64-bit vectors.
+define half @extractelement_v4f16(<4 x half>* %a) #0 {
+; CHECK-LABEL: extractelement_v4f16:
+; CHECK:         ldr d0, [x0]
+; CHECK-NEXT:    mov h0, v0.h[2]
+; CHECK-NEXT:    ret
+    %op1 = load <4 x half>, <4 x half>* %a
+    %r = extractelement <4 x half> %op1, i64 2
+    ret half %r
+}
+
+; Don't use SVE for 128-bit vectors.
+define half @extractelement_v8f16(<8 x half>* %a) #0 {
+; CHECK-LABEL: extractelement_v8f16:
+; CHECK:         ldr h0, [x0, #4]
+; CHECK-NEXT:    ret
+    %op1 = load <8 x half>, <8 x half>* %a
+    %r = extractelement <8 x half> %op1, i64 2
+    ret half %r
+}
+
+define half @extractelement_v16f16(<16 x half>* %a) #0 {
+; CHECK-LABEL: extractelement_v16f16:
+; VBITS_GE_256:         ptrue   p0.h, vl16
+; VBITS_GE_256-NEXT:    ld1h    { z0.h }, p0/z, [x0]
+; VBITS_GE_256-NEXT:    mov z0.h, z0.h[2]
+; VBITS_GE_256-NEXT:    ret
+    %op1 = load <16 x half>, <16 x half>* %a
+    %r = extractelement <16 x half> %op1, i64 2
+    ret half %r
+}
+
+define half @extractelement_v32f16(<32 x half>* %a) #0 {
+; CHECK-LABEL: extractelement_v32f16:
+; VBITS_GE_512:         ptrue   p0.h, vl32
+; VBITS_GE_512-NEXT:    ld1h    { z0.h }, p0/z, [x0]
+; VBITS_GE_512-NEXT:    mov z0.h, z0.h[2]
+; VBITS_GE_512-NEXT:    ret
+    %op1 = load <32 x half>, <32 x half>* %a
+    %r = extractelement <32 x half> %op1, i64 2
+    ret half %r
+}
+
+define half @extractelement_v64f16(<64 x half>* %a) #0 {
+; CHECK-LABEL: extractelement_v64f16:
+; VBITS_GE_1024:         ptrue   p0.h, vl64
+; VBITS_GE_1024-NEXT:    ld1h    { z0.h }, p0/z, [x0]
+; VBITS_GE_1024-NEXT:    mov z0.h, z0.h[2]
+; VBITS_GE_1024-NEXT:    ret
+    %op1 = load <64 x half>, <64 x half>* %a
+    %r = extractelement <64 x half> %op1, i64 2
+    ret half %r
+}
+
+define half @extractelement_v128f16(<128 x half>* %a) #0 {
+; CHECK-LABEL: extractelement_v128f16:
+; VBITS_GE_2048:      ptrue   p0.h, vl128
+; VBITS_GE_2048-NEXT: ld1h    { z0.h }, p0/z, [x0]
+; VBITS_GE_2048-NEXT: mov z0.h, z0.h[2]
+; VBITS_GE_2048-NEXT: ret
+    %op1 = load <128 x half>, <128 x half>* %a
+    %r = extractelement <128 x half> %op1, i64 2
+    ret half %r
+}
+
+define float @extractelement_v4f32(<4 x float>* %a) #0 {
+; CHECK-LABEL: extractelement_v4f32:
+; CHECK:         ldr s0, [x0, #8]
+; CHECK-NEXT:    ret
+    %op1 = load <4 x float>, <4 x float>* %a
+    %r = extractelement <4 x float> %op1, i64 2
+    ret float %r
+}
+
+define float @extractelement_v8f32(<8 x float>* %a) #0 {
+; CHECK-LABEL: extractelement_v8f32:
+; VBITS_GE_256:         ptrue   p0.s, vl8
+; VBITS_GE_256-NEXT:    ld1w    { z0.s }, p0/z, [x0]
+; VBITS_GE_256-NEXT:    mov z0.s, z0.s[2]
+; VBITS_GE_256-NEXT:    ret
+    %op1 = load <8 x float>, <8 x float>* %a
+    %r = extractelement <8 x float> %op1, i64 2
+    ret float %r
+}
+
+define float @extractelement_v16f32(<16 x float>* %a) #0 {
+; CHECK-LABEL: extractelement_v16f32:
+; VBITS_GE_512:         ptrue   p0.s, vl16
+; VBITS_GE_512-NEXT:    ld1w    { z0.s }, p0/z, [x0]
+; VBITS_GE_512-NEXT:    mov z0.s, z0.s[2]
+; VBITS_GE_512-NEXT:    ret
+    %op1 = load <16 x float>, <16 x float>* %a
+    %r = extractelement <16 x float> %op1, i64 2
+    ret float %r
+}
+
+define float @extractelement_v32f32(<32 x float>* %a) #0 {
+; CHECK-LABEL: extractelement_v32f32:
+; VBITS_GE_1024:        ptrue   p0.s, vl32
+; VBITS_GE_1024-NEXT:   ld1w    { z0.s }, p0/z, [x0]
+; VBITS_GE_1024-NEXT:   mov z0.s, z0.s[2]
+; VBITS_GE_1024-NEXT:   ret
+    %op1 = load <32 x float>, <32 x float>* %a
+    %r = extractelement <32 x float> %op1, i64 2
+    ret float %r
+}
+
+define float @extractelement_v64f32(<64 x float>* %a) #0 {
+; CHECK-LABEL: extractelement_v64f32:
+; VBITS_GE_2048:        ptrue   p0.s, vl64
+; VBITS_GE_2048-NEXT:   ld1w    { z0.s }, p0/z, [x0]
+; VBITS_GE_2048-NEXT:   mov z0.s, z0.s[2]
+; VBITS_GE_2048-NEXT:   ret
+    %op1 = load <64 x float>, <64 x float>* %a
+    %r = extractelement <64 x float> %op1, i64 2
+    ret float %r
+}
+
+define double @extractelement_v4f64(<4 x double>* %a) #0 {
+; CHECK-LABEL: extractelement_v4f64:
+; VBITS_GE_256:         ptrue   p0.d, vl4
+; VBITS_GE_256-NEXT:    ld1d    { z0.d }, p0/z, [x0]
+; VBITS_GE_256-NEXT:    mov z0.d, z0.d[2]
+; VBITS_GE_256-NEXT:    ret
+    %op1 = load <4 x double>, <4 x double>* %a
+    %r = extractelement <4 x double> %op1, i64 2
+    ret double %r
+}
+
+define double @extractelement_v8f64(<8 x double>* %a) #0 {
+; CHECK-LABEL: extractelement_v8f64:
+; VBITS_GE_512:         ptrue   p0.d, vl8
+; VBITS_GE_512-NEXT:    ld1d    { z0.d }, p0/z, [x0]
+; VBITS_GE_512-NEXT:    mov z0.d, z0.d[2]
+; VBITS_GE_512-NEXT:    ret
+    %op1 = load <8 x double>, <8 x double>* %a
+    %r = extractelement <8 x double> %op1, i64 2
+    ret double %r
+}
+
+define double @extractelement_v16f64(<16 x double>* %a) #0 {
+; CHECK-LABEL: extractelement_v16f64:
+; VBITS_GE_1024:         ptrue   p0.d, vl16
+; VBITS_GE_1024-NEXT:    ld1d    { z0.d }, p0/z, [x0]
+; VBITS_GE_1024-NEXT:    mov z0.d, z0.d[2]
+; VBITS_GE_1024-NEXT:    ret
+    %op1 = load <16 x double>, <16 x double>* %a
+    %r = extractelement <16 x double> %op1, i64 2
+    ret double %r
+}
+
+define double @extractelement_v32f64(<32 x double>* %a) #0 {
+; CHECK-LABEL: extractelement_v32f64:
+; VBITS_GE_2048:         ptrue   p0.d, vl32
+; VBITS_GE_2048-NEXT:    ld1d    { z0.d }, p0/z, [x0]
+; VBITS_GE_2048-NEXT:    mov z0.d, z0.d[2]
+; VBITS_GE_2048-NEXT:    ret
+    %op1 = load <32 x double>, <32 x double>* %a
+    %r = extractelement <32 x double> %op1, i64 2
+    ret double %r
+}
+
+attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll
@@ -31,7 +31,7 @@
 
 define <8 x half> @fptrunc_v8f32_v8f16(<8 x float>* %in) #0 {
 ; CHECK-LABEL: fptrunc_v8f32_v8f16:
-; CHECK-COUNT-8: fcvt h{{[0-9]}}, s{{[0-9]}}
+; CHECK-COUNT-8: fcvt h{{[0-9]+}}, s{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <8 x float>, <8 x float>* %in
@@ -41,7 +41,7 @@
 
 define void @fptrunc_v16f32_v16f16(<16 x float>* %in, <16 x half>* %out) #0 {
 ; CHECK-LABEL: fptrunc_v16f32_v16f16:
-; CHECK-COUNT-16: fcvt h{{[0-9]}}, s{{[0-9]}}
+; CHECK-COUNT-16: fcvt h{{[0-9]+}}, s{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <16 x float>, <16 x float>* %in
@@ -52,7 +52,7 @@
 
 define void @fptrunc_v32f32_v32f16(<32 x float>* %in, <32 x half>* %out) #0 {
 ; CHECK-LABEL: fptrunc_v32f32_v32f16:
-; CHECK-COUNT-32: fcvt h{{[0-9]}}, s{{[0-9]}}
+; CHECK-COUNT-32: fcvt h{{[0-9]+}}, s{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <32 x float>, <32 x float>* %in
@@ -63,7 +63,7 @@
 
 define void @fptrunc_v64f32_v64f16(<64 x float>* %in, <64 x half>* %out) #0 {
 ; CHECK-LABEL: fptrunc_v64f32_v64f16:
-; CHECK-COUNT-64: fcvt h{{[0-9]}}, s{{[0-9]}}
+; CHECK-COUNT-64: fcvt h{{[0-9]+}}, s{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <64 x float>, <64 x float>* %in
@@ -78,7 +78,7 @@
 
 define <4 x half> @fptrunc_v4f64_v4f16(<4 x double>* %in) #0 {
 ; CHECK-LABEL: fptrunc_v4f64_v4f16:
-; CHECK-COUNT-4: fcvt h{{[0-9]}}, d{{[0-9]}}
+; CHECK-COUNT-4: fcvt h{{[0-9]+}}, d{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <4 x double>, <4 x double>* %in
@@ -88,7 +88,7 @@
 
 define <8 x half> @fptrunc_v8f64_v8f16(<8 x double>* %in) #0 {
 ; CHECK-LABEL: fptrunc_v8f64_v8f16:
-; CHECK-COUNT-8: fcvt h{{[0-9]}}, d{{[0-9]}}
+; CHECK-COUNT-8: fcvt h{{[0-9]+}}, d{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <8 x double>, <8 x double>* %in
@@ -98,7 +98,7 @@
 
 define void @fptrunc_v16f64_v16f16(<16 x double>* %in, <16 x half>* %out) #0 {
 ; CHECK-LABEL: fptrunc_v16f64_v16f16:
-; CHECK-COUNT-16: fcvt h{{[0-9]}}, d{{[0-9]}}
+; CHECK-COUNT-16: fcvt h{{[0-9]+}}, d{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <16 x double>, <16 x double>* %in
@@ -109,7 +109,7 @@
 
 define void @fptrunc_v32f64_v32f16(<32 x double>* %in, <32 x half>* %out) #0 {
 ; CHECK-LABEL: fptrunc_v32f64_v32f16:
-; CHECK-COUNT-32: fcvt h{{[0-9]}}, d{{[0-9]}}
+; CHECK-COUNT-32: fcvt h{{[0-9]+}}, d{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <32 x double>, <32 x double>* %in
@@ -124,7 +124,7 @@
 
 define <4 x float> @fptrunc_v4f64_v4f32(<4 x double>* %in) #0 {
 ; CHECK-LABEL: fptrunc_v4f64_v4f32:
-; CHECK-COUNT-4: fcvt s{{[0-9]}}, d{{[0-9]}}
+; CHECK-COUNT-4: fcvt s{{[0-9]+}}, d{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <4 x double>, <4 x double>* %in
@@ -134,7 +134,7 @@
 
 define void @fptrunc_v8f64_v8f32(<8 x double>* %in, <8 x float>* %out) #0 {
 ; CHECK-LABEL: fptrunc_v8f64_v8f32:
-; CHECK-COUNT-8: fcvt s{{[0-9]}}, d{{[0-9]}}
+; CHECK-COUNT-8: fcvt s{{[0-9]+}}, d{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <8 x double>, <8 x double>* %in
@@ -145,7 +145,7 @@
 
 define void @fptrunc_v16f64_v16f32(<16 x double>* %in, <16 x float>* %out) #0 {
 ; CHECK-LABEL: fptrunc_v16f64_v16f32:
-; CHECK-COUNT-16: fcvt s{{[0-9]}}, d{{[0-9]}}
+; CHECK-COUNT-16: fcvt s{{[0-9]+}}, d{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <16 x double>, <16 x double>* %in
@@ -156,7 +156,7 @@
 
 define void @fptrunc_v32f64_v32f32(<32 x double>* %in, <32 x float>* %out) #0 {
 ; CHECK-LABEL: fptrunc_v32f64_v32f32:
-; CHECK-COUNT-32: fcvt s{{[0-9]}}, d{{[0-9]}}
+; CHECK-COUNT-32: fcvt s{{[0-9]+}}, d{{[0-9]+}}
 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <32 x double>, <32 x double>* %in