Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -996,6 +996,9 @@
 // Match X > -1, the canonical form of X >= 0, to the bgez pattern.
 def : Pat<(brcond (XLenVT (setgt GPR:$rs1, -1)), bb:$imm12),
           (BGE GPR:$rs1, X0, bb:$imm12)>;
+// Lower (a < 1) as (0 >= a) into the bgez pattern.
+def : Pat<(brcond (XLenVT (setlt GPR:$lhs, 1)), bb:$imm12),
+	  (BGE X0, GPR:$lhs, bb:$imm12)>;
 
 let isBarrier = 1, isBranch = 1, isTerminator = 1 in
 def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
Index: llvm/test/CodeGen/RISCV/branch.ll
===================================================================
--- llvm/test/CodeGen/RISCV/branch.ll
+++ llvm/test/CodeGen/RISCV/branch.ll
@@ -43,7 +43,10 @@
 ; RV32I-NEXT:    bgez a0, .LBB0_13
 ; RV32I-NEXT:  # %bb.12: # %test13
 ; RV32I-NEXT:    lw a0, 0(a1)
-; RV32I-NEXT:  .LBB0_13: # %end
+; RV32I-NEXT:  # %bb.13: # %test14
+; RV32I-NEXT:    lw a0, 0(a1)
+; RV32I-NEXT:    bge zero, a0, .LBB0_13
+; RV32I-NEXT:  .LBB0_14: # %end
 ; RV32I-NEXT:    ret
   %val1 = load volatile i32, i32* %b
   %tst1 = icmp eq i32 %val1, %a
@@ -114,6 +117,12 @@
   %val13 = load volatile i32, i32* %b
   br label %end
 
+; Check that we use bgez (0 >= X) for X < 1
+test14:
+  %val14 = load volatile i32, i32* %b
+  %tst14 = icmp slt i32 %val14, 1
+  br i1 %tst14, label %end, label %test14
+
 end:
   ret void
 }