Index: llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td +++ llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td @@ -245,6 +245,7 @@ } defm : int_cond_alias<"a", 0b1000>; +defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual defm : int_cond_alias<"n", 0b0000>; defm : int_cond_alias<"ne", 0b1001>; defm : int_cond_alias<"nz", 0b1001>; // same as ne @@ -266,6 +267,7 @@ defm : int_cond_alias<"vs", 0b0111>; defm : fp_cond_alias<"a", 0b0000>; +defm : fp_cond_alias<"", 0b0000>; // same as a; gnu asm, not in manual defm : fp_cond_alias<"n", 0b1000>; defm : fp_cond_alias<"u", 0b0111>; defm : fp_cond_alias<"g", 0b0110>; @@ -284,7 +286,16 @@ defm : fp_cond_alias<"ule", 0b1110>; defm : fp_cond_alias<"o", 0b1111>; -// Instruction aliases for JMPL. +// Section A.3 Synthetic Instructions + +// Most are marked as Emit=0, so that they are not used for disassembly. This is +// an aesthetic issue, but the chosen policy is to typically prefer using the +// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp, +// call, tst, ret, retl. + +// Note: cmp is handled in SparcInstrInfo. +// jmp/call/ret/retl have special case handling for output in +// SparcInstPrinter.cpp // jmp addr -> jmpl addr, %g0 def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>; @@ -294,28 +305,129 @@ def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>; def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>; -// retl -> RETL 8 -def : InstAlias<"retl", (RETL 8)>; +// tst reg -> orcc %g0, reg, %g0 +def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>; -// ret -> RET 8 +// ret -> jmpl %i7+8, %g0 (aka RET 8) def : InstAlias<"ret", (RET 8)>; -// mov reg, rd -> or %g0, reg, rd -def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; +// retl -> jmpl %o7+8, %g0 (aka RETL 8) +def : InstAlias<"retl", (RETL 8)>; -// mov simm13, rd -> or %g0, simm13, rd -def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; +// restore -> restore %g0, %g0, %g0 +def : InstAlias<"restore", (RESTORErr G0, G0, G0)>; -// flush -> flush %g0 -def : InstAlias<"flush", (FLUSH), 0>; +// save -> restore %g0, %g0, %g0 +def : InstAlias<"save", (SAVErr G0, G0, G0)>; // set value, rd // (turns into a sequence of sethi+or, depending on the value) // def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">; -// restore -> restore %g0, %g0, %g0 -def : InstAlias<"restore", (RESTORErr G0, G0, G0)>; +// not rd -> xnor rd, %g0, rd +def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>; + +// not reg, rd -> xnor reg, %g0, rd +def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>; + +// neg rd -> sub %g0, rd, rd +def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>; + +// neg reg, rd -> sub %g0, reg, rd +def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>; + +// inc rd -> add rd, 1, rd +def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>; + +// inc simm13, rd -> add rd, simm13, rd +def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; + +// inccc rd -> addcc rd, 1, rd +def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>; + +// inccc simm13, rd -> addcc rd, simm13, rd +def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; + +// dec rd -> sub rd, 1, rd +def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>; + +// dec simm13, rd -> sub rd, simm13, rd +def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; + +// deccc rd -> subcc rd, 1, rd +def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>; + +// deccc simm13, rd -> subcc rd, simm13, rd +def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; + +// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0 +def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>; +def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>; + +// bset reg_or_imm, rd -> or rd,reg_or_imm,rd +def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>; +def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; + +// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd +def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>; +def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; + +// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd +def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>; +def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; + + +// clr rd -> or %g0, %g0, rd +def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>; + +// clr{b,h,} [addr] -> st{b,h,} %g0, [addr] +def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>; +def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>; +def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>; +def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>; +def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>; +def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>; + + +// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd +def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; +def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; + +// mov specialreg, rd -> rd specialreg, rd +def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>; +def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>; +def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>; +def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>; + +// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg +def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>; +def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>; +def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>; +def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>; +def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>; +def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>; +def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>; +def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>; + +// End of Section A.3 + +// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg +// (aka: omit the first arg when it's g0. This is not in the manual, but is +// supported by gnu and solaris as) +def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>; +def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>; +def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>; +def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>; +def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>; +def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>; +def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>; +def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>; + + +// flush -> flush %g0 +def : InstAlias<"flush", (FLUSH), 0>; + def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>; Index: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td @@ -536,6 +536,7 @@ let Uses = [ICC] in defm SUBC : F3_12np <"subx", 0b001100>; +// cmp (from Section A.3) is a specialized alias for subcc let Defs = [ICC], rd = 0 in { def CMPrr : F3_1<2, 0b010100, (outs), (ins IntRegs:$rs1, IntRegs:$rs2), Index: llvm/trunk/test/MC/Sparc/sparc-alu-instructions.s =================================================================== --- llvm/trunk/test/MC/Sparc/sparc-alu-instructions.s +++ llvm/trunk/test/MC/Sparc/sparc-alu-instructions.s @@ -76,8 +76,8 @@ ! CHECK: mov 255, %g3 ! encoding: [0x86,0x10,0x20,0xff] mov 0xff, %g3 - ! CHECK: restore ! encoding: [0x81,0xe8,0x00,0x00] - restore %g0, %g0, %g0 + ! CHECK: restore %g0, %g0, %g1 ! encoding: [0x83,0xe8,0x00,0x00] + restore %g0, %g0, %g1 ! CHECK: addx %g2, %g1, %g3 ! encoding: [0x86,0x40,0x80,0x01] addx %g2, %g1, %g3 Index: llvm/trunk/test/MC/Sparc/sparc-synthetic-instructions.s =================================================================== --- llvm/trunk/test/MC/Sparc/sparc-synthetic-instructions.s +++ llvm/trunk/test/MC/Sparc/sparc-synthetic-instructions.s @@ -2,6 +2,26 @@ ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s ! Section A.3 Synthetic Instructions + ! CHECK: cmp %g1, %g2 ! encoding: [0x80,0xa0,0x40,0x02] + cmp %g1, %g2 + ! CHECK: cmp %g1, 5 ! encoding: [0x80,0xa0,0x60,0x05] + cmp %g1, 5 + + ! jmp and call are tested in sparc-ctrl-instructions. + + ! CHECK: tst %g1 ! encoding: [0x80,0x90,0x40,0x00] + tst %g1 + + ! CHECK: ret ! encoding: [0x81,0xc7,0xe0,0x08] + ret + ! CHECK: retl ! encoding: [0x81,0xc3,0xe0,0x08] + retl + + ! CHECK: restore ! encoding: [0x81,0xe8,0x00,0x00] + restore + ! CHECK: save ! encoding: [0x81,0xe0,0x00,0x00] + save + ! CHECK: sethi %hi(40000), %g1 ! encoding: [0x03,0b00AAAAAA,A,A] ! CHECK: ! fixup A - offset: 0, value: %hi(40000), kind: fixup_sparc_hi22 ! CHECK: or %g1, %lo(40000), %g1 ! encoding: [0x82,0x10,0b011000AA,A] @@ -10,8 +30,116 @@ ! CHECK: mov %lo(1), %g1 ! encoding: [0x82,0x10,0b001000AA,A] ! CHECK: ! fixup A - offset: 0, value: %lo(1), kind: fixup_sparc_lo10 set 1, %g1 - ! CHECK: sethi %hi(32768), %g1 ! encoding: [0x03,0b00AAAAAA,A,A] ! CHECK: ! fixup A - offset: 0, value: %hi(32768), kind: fixup_sparc_hi22 set 32768, %g1 + ! CHECK: xnor %g1, %g0, %g2 ! encoding: [0x84,0x38,0x40,0x00] + not %g1, %g2 + ! CHECK: xnor %g1, %g0, %g1 ! encoding: [0x82,0x38,0x40,0x00] + not %g1 + + ! CHECK: sub %g0, %g1, %g2 ! encoding: [0x84,0x20,0x00,0x01] + neg %g1, %g2 + ! CHECK: sub %g0, %g1, %g1 ! encoding: [0x82,0x20,0x00,0x01] + neg %g1 + + ! CHECK: add %g1, 1, %g1 ! encoding: [0x82,0x00,0x60,0x01] + inc %g1 + ! CHECK: add %g1, 55, %g1 ! encoding: [0x82,0x00,0x60,0x37] + inc 55, %g1 + ! CHECK: addcc %g1, 1, %g1 ! encoding: [0x82,0x80,0x60,0x01] + inccc %g1 + ! CHECK: addcc %g1, 55, %g1 ! encoding: [0x82,0x80,0x60,0x37] + inccc 55, %g1 + + ! CHECK: sub %g1, 1, %g1 ! encoding: [0x82,0x20,0x60,0x01] + dec %g1 + ! CHECK: sub %g1, 55, %g1 ! encoding: [0x82,0x20,0x60,0x37] + dec 55, %g1 + ! CHECK: subcc %g1, 1, %g1 ! encoding: [0x82,0xa0,0x60,0x01] + deccc %g1 + ! CHECK: subcc %g1, 55, %g1 ! encoding: [0x82,0xa0,0x60,0x37] + deccc 55, %g1 + + ! CHECK: andcc %g2, %g1, %g0 ! encoding: [0x80,0x88,0x80,0x01] + btst %g1, %g2 + ! CHECK: andcc %g2, 4, %g0 ! encoding: [0x80,0x88,0xa0,0x04] + btst 4, %g2 + ! CHECK: or %g2, %g1, %g2 ! encoding: [0x84,0x10,0x80,0x01] + bset %g1, %g2 + ! CHECK: or %g2, 4, %g2 ! encoding: [0x84,0x10,0xa0,0x04] + bset 4, %g2 + ! CHECK: andn %g2, %g1, %g2 ! encoding: [0x84,0x28,0x80,0x01] + bclr %g1, %g2 + ! CHECK: andn %g2, 4, %g2 ! encoding: [0x84,0x28,0xa0,0x04] + bclr 4, %g2 + ! CHECK: xor %g2, %g1, %g2 ! encoding: [0x84,0x18,0x80,0x01] + btog %g1, %g2 + ! CHECK: xor %g2, 4, %g2 ! encoding: [0x84,0x18,0xa0,0x04] + btog 4, %g2 + + ! CHECK: mov %g0, %g1 ! encoding: [0x82,0x10,0x00,0x00] + clr %g1 + ! CHECK: stb %g0, [%g1+%g2] ! encoding: [0xc0,0x28,0x40,0x02] + clrb [%g1+%g2] + ! CHECK: sth %g0, [%g1+%g2] ! encoding: [0xc0,0x30,0x40,0x02] + clrh [%g1+%g2] + ! CHECK: st %g0, [%g1+%g2] ! encoding: [0xc0,0x20,0x40,0x02] + clr [%g1+%g2] + + ! mov reg_or_imm,reg tested in sparc-alu-instructions.s + + ! CHECK: rd %y, %i0 ! encoding: [0xb1,0x40,0x00,0x00] + mov %y, %i0 + ! CHECK: rd %asr1, %i0 ! encoding: [0xb1,0x40,0x40,0x00] + mov %asr1, %i0 + ! CHECK: rd %psr, %i0 ! encoding: [0xb1,0x48,0x00,0x00] + mov %psr, %i0 + ! CHECK: rd %wim, %i0 ! encoding: [0xb1,0x50,0x00,0x00] + mov %wim, %i0 + ! CHECK: rd %tbr, %i0 ! encoding: [0xb1,0x58,0x00,0x00] + mov %tbr, %i0 + + ! CHECK: wr %g0, %i0, %y ! encoding: [0x81,0x80,0x00,0x18] + mov %i0, %y + ! CHECK: wr %g0, 5, %y ! encoding: [0x81,0x80,0x20,0x05] + mov 5, %y + ! CHECK: wr %g0, %i0, %asr15 ! encoding: [0x9f,0x80,0x00,0x18] + mov %i0, %asr15 + ! CHECK: wr %g0, 5, %asr15 ! encoding: [0x9f,0x80,0x20,0x05] + mov 5, %asr15 + ! CHECK: wr %g0, %i0, %psr ! encoding: [0x81,0x88,0x00,0x18] + mov %i0, %psr + ! CHECK: wr %g0, 5, %psr ! encoding: [0x81,0x88,0x20,0x05] + mov 5, %psr + ! CHECK: wr %g0, %i0, %wim ! encoding: [0x81,0x90,0x00,0x18] + mov %i0, %wim + ! CHECK: wr %g0, 5, %wim ! encoding: [0x81,0x90,0x20,0x05] + mov 5, %wim + ! CHECK: wr %g0, %i0, %tbr ! encoding: [0x81,0x98,0x00,0x18] + mov %i0, %tbr + ! CHECK: wr %g0, 5, %tbr ! encoding: [0x81,0x98,0x20,0x05] + mov 5, %tbr + +! Other aliases + ! CHECK: wr %g0, %i0, %y ! encoding: [0x81,0x80,0x00,0x18] + wr %i0, %y + ! CHECK: wr %g0, 5, %y ! encoding: [0x81,0x80,0x20,0x05] + wr 5, %y + ! CHECK: wr %g0, %i0, %asr15 ! encoding: [0x9f,0x80,0x00,0x18] + wr %i0, %asr15 + ! CHECK: wr %g0, 5, %asr15 ! encoding: [0x9f,0x80,0x20,0x05] + wr 5, %asr15 + ! CHECK: wr %g0, %i0, %psr ! encoding: [0x81,0x88,0x00,0x18] + wr %i0, %psr + ! CHECK: wr %g0, 5, %psr ! encoding: [0x81,0x88,0x20,0x05] + wr 5, %psr + ! CHECK: wr %g0, %i0, %wim ! encoding: [0x81,0x90,0x00,0x18] + wr %i0, %wim + ! CHECK: wr %g0, 5, %wim ! encoding: [0x81,0x90,0x20,0x05] + wr 5, %wim + ! CHECK: wr %g0, %i0, %tbr ! encoding: [0x81,0x98,0x00,0x18] + wr %i0, %tbr + ! CHECK: wr %g0, 5, %tbr ! encoding: [0x81,0x98,0x20,0x05] + wr 5, %tbr