diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -84,6 +84,8 @@ FMA_PRED, FMAXNM_PRED, FMINNM_PRED, + FMAX_PRED, + FMIN_PRED, FMUL_PRED, FSUB_PRED, MUL_PRED, diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1168,7 +1168,9 @@ setOperationAction(ISD::FADD, VT, Custom); setOperationAction(ISD::FDIV, VT, Custom); setOperationAction(ISD::FMA, VT, Custom); + setOperationAction(ISD::FMAXIMUM, VT, Custom); setOperationAction(ISD::FMAXNUM, VT, Custom); + setOperationAction(ISD::FMINIMUM, VT, Custom); setOperationAction(ISD::FMINNUM, VT, Custom); setOperationAction(ISD::FMUL, VT, Custom); setOperationAction(ISD::FNEG, VT, Custom); @@ -1392,7 +1394,9 @@ setOperationAction(ISD::FDIV, VT, Custom); setOperationAction(ISD::FFLOOR, VT, Custom); setOperationAction(ISD::FMA, VT, Custom); + setOperationAction(ISD::FMAXIMUM, VT, Custom); setOperationAction(ISD::FMAXNUM, VT, Custom); + setOperationAction(ISD::FMINIMUM, VT, Custom); setOperationAction(ISD::FMINNUM, VT, Custom); setOperationAction(ISD::FMUL, VT, Custom); setOperationAction(ISD::FNEARBYINT, VT, Custom); @@ -1875,9 +1879,11 @@ MAKE_CASE(AArch64ISD::FADDV_PRED) MAKE_CASE(AArch64ISD::FDIV_PRED) MAKE_CASE(AArch64ISD::FMA_PRED) + MAKE_CASE(AArch64ISD::FMAX_PRED) MAKE_CASE(AArch64ISD::FMAXV_PRED) MAKE_CASE(AArch64ISD::FMAXNM_PRED) MAKE_CASE(AArch64ISD::FMAXNMV_PRED) + MAKE_CASE(AArch64ISD::FMIN_PRED) MAKE_CASE(AArch64ISD::FMINV_PRED) MAKE_CASE(AArch64ISD::FMINNM_PRED) MAKE_CASE(AArch64ISD::FMINNMV_PRED) @@ -4498,8 +4504,12 @@ return LowerToScalableOp(Op, DAG); case ISD::SUB: return LowerToPredicatedOp(Op, DAG, AArch64ISD::SUB_PRED); + case ISD::FMAXIMUM: + return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMAX_PRED); case ISD::FMAXNUM: return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMAXNM_PRED); + case ISD::FMINIMUM: + return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMIN_PRED); case ISD::FMINNUM: return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMINNM_PRED); case ISD::VSELECT: diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -182,6 +182,8 @@ def AArch64fma_p : SDNode<"AArch64ISD::FMA_PRED", SDT_AArch64FMA>; def AArch64fmaxnm_p : SDNode<"AArch64ISD::FMAXNM_PRED", SDT_AArch64Arith>; def AArch64fminnm_p : SDNode<"AArch64ISD::FMINNM_PRED", SDT_AArch64Arith>; +def AArch64fmax_p : SDNode<"AArch64ISD::FMAX_PRED", SDT_AArch64Arith>; +def AArch64fmin_p : SDNode<"AArch64ISD::FMIN_PRED", SDT_AArch64Arith>; def AArch64fmul_p : SDNode<"AArch64ISD::FMUL_PRED", SDT_AArch64Arith>; def AArch64fsub_p : SDNode<"AArch64ISD::FSUB_PRED", SDT_AArch64Arith>; def AArch64lsl_p : SDNode<"AArch64ISD::SHL_PRED", SDT_AArch64Arith>; @@ -429,6 +431,8 @@ defm FMUL_ZPZZ : sve_fp_bin_pred_hfd; defm FMAXNM_ZPZZ : sve_fp_bin_pred_hfd; defm FMINNM_ZPZZ : sve_fp_bin_pred_hfd; + defm FMAX_ZPZZ : sve_fp_bin_pred_hfd; + defm FMIN_ZPZZ : sve_fp_bin_pred_hfd; defm FDIV_ZPZZ : sve_fp_bin_pred_hfd; let Predicates = [HasSVE, UseExperimentalZeroingPseudos] in { diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll @@ -580,6 +580,566 @@ ret void } +; +; FMAX +; + +; Don't use SVE for 64-bit vectors. +define <4 x half> @fmax_v4f16(<4 x half> %op1, <4 x half> %op2) #0 { +; CHECK-LABEL: fmax_v4f16: +; CHECK: fmax v0.4h, v0.4h, v1.4h +; CHECK-NEXT: ret + %res = call <4 x half> @llvm.maximum.v4f16(<4 x half> %op1, <4 x half> %op2) + ret <4 x half> %res +} + +; Don't use SVE for 128-bit vectors. +define <8 x half> @fmax_v8f16(<8 x half> %op1, <8 x half> %op2) #0 { +; CHECK-LABEL: fmax_v8f16: +; CHECK: fmax v0.8h, v0.8h, v1.8h +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.maximum.v8f16(<8 x half> %op1, <8 x half> %op2) + ret <8 x half> %res +} + +define void @fmax_v16f16(<16 x half>* %a, <16 x half>* %b) #0 { +; CHECK-LABEL: fmax_v16f16: +; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 +; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] +; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] +; CHECK-NEXT: fmax [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h +; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; CHECK-NEXT: ret + %op1 = load <16 x half>, <16 x half>* %a + %op2 = load <16 x half>, <16 x half>* %b + %res = call <16 x half> @llvm.maximum.v16f16(<16 x half> %op1, <16 x half> %op2) + store <16 x half> %res, <16 x half>* %a + ret void +} + +define void @fmax_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +; CHECK-LABEL: fmax_v32f16: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 +; VBITS_GE_512-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_512-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] +; VBITS_GE_512-NEXT: fmax [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h +; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: add x[[B_HI:[0-9]+]], x1, #32 +; VBITS_EQ_256-DAG: ld1h { [[OP1_LO:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1h { [[OP1_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: ld1h { [[OP2_LO:z[0-9]+]].h }, [[PG]]/z, [x1] +; VBITS_EQ_256-DAG: ld1h { [[OP2_HI:z[0-9]+]].h }, [[PG]]/z, [x[[B_HI]]] +; VBITS_EQ_256-DAG: fmax [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[OP1_LO]].h, [[OP2_LO]].h +; VBITS_EQ_256-DAG: fmax [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[OP1_HI]].h, [[OP2_HI]].h +; VBITS_EQ_256-DAG: st1h { [[RES_LO]].h }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1h { [[RES_HI]].h }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op1 = load <32 x half>, <32 x half>* %a + %op2 = load <32 x half>, <32 x half>* %b + %res = call <32 x half> @llvm.maximum.v32f16(<32 x half> %op1, <32 x half> %op2) + store <32 x half> %res, <32 x half>* %a + ret void +} + +define void @fmax_v64f16(<64 x half>* %a, <64 x half>* %b) #0 { +; CHECK-LABEL: fmax_v64f16: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 +; VBITS_GE_1024-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_1024-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] +; VBITS_GE_1024-NEXT: fmax [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h +; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op1 = load <64 x half>, <64 x half>* %a + %op2 = load <64 x half>, <64 x half>* %b + %res = call <64 x half> @llvm.maximum.v64f16(<64 x half> %op1, <64 x half> %op2) + store <64 x half> %res, <64 x half>* %a + ret void +} + +define void @fmax_v128f16(<128 x half>* %a, <128 x half>* %b) #0 { +; CHECK-LABEL: fmax_v128f16: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 +; VBITS_GE_2048-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_2048-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] +; VBITS_GE_2048-NEXT: fmax [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h +; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op1 = load <128 x half>, <128 x half>* %a + %op2 = load <128 x half>, <128 x half>* %b + %res = call <128 x half> @llvm.maximum.v128f16(<128 x half> %op1, <128 x half> %op2) + store <128 x half> %res, <128 x half>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <2 x float> @fmax_v2f32(<2 x float> %op1, <2 x float> %op2) #0 { +; CHECK-LABEL: fmax_v2f32: +; CHECK: fmax v0.2s, v0.2s, v1.2s +; CHECK-NEXT: ret + %res = call <2 x float> @llvm.maximum.v2f32(<2 x float> %op1, <2 x float> %op2) + ret <2 x float> %res +} + +; Don't use SVE for 128-bit vectors. +define <4 x float> @fmax_v4f32(<4 x float> %op1, <4 x float> %op2) #0 { +; CHECK-LABEL: fmax_v4f32: +; CHECK: fmax v0.4s, v0.4s, v1.4s +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.maximum.v4f32(<4 x float> %op1, <4 x float> %op2) + ret <4 x float> %res +} + +define void @fmax_v8f32(<8 x float>* %a, <8 x float>* %b) #0 { +; CHECK-LABEL: fmax_v8f32: +; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 +; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] +; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] +; CHECK-NEXT: fmax [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s +; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; CHECK-NEXT: ret + %op1 = load <8 x float>, <8 x float>* %a + %op2 = load <8 x float>, <8 x float>* %b + %res = call <8 x float> @llvm.maximum.v8f32(<8 x float> %op1, <8 x float> %op2) + store <8 x float> %res, <8 x float>* %a + ret void +} + +define void @fmax_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +; CHECK-LABEL: fmax_v16f32: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 +; VBITS_GE_512-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_512-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] +; VBITS_GE_512-NEXT: fmax [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s +; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: add x[[B_HI:[0-9]+]], x1, #32 +; VBITS_EQ_256-DAG: ld1w { [[OP1_LO:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1w { [[OP1_HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: ld1w { [[OP2_LO:z[0-9]+]].s }, [[PG]]/z, [x1] +; VBITS_EQ_256-DAG: ld1w { [[OP2_HI:z[0-9]+]].s }, [[PG]]/z, [x[[B_HI]]] +; VBITS_EQ_256-DAG: fmax [[RES_LO:z[0-9]+]].s, [[PG]]/m, [[OP1_LO]].s, [[OP2_LO]].s +; VBITS_EQ_256-DAG: fmax [[RES_HI:z[0-9]+]].s, [[PG]]/m, [[OP1_HI]].s, [[OP2_HI]].s +; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op1 = load <16 x float>, <16 x float>* %a + %op2 = load <16 x float>, <16 x float>* %b + %res = call <16 x float> @llvm.maximum.v16f32(<16 x float> %op1, <16 x float> %op2) + store <16 x float> %res, <16 x float>* %a + ret void +} + +define void @fmax_v32f32(<32 x float>* %a, <32 x float>* %b) #0 { +; CHECK-LABEL: fmax_v32f32: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32 +; VBITS_GE_1024-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_1024-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] +; VBITS_GE_1024-NEXT: fmax [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s +; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op1 = load <32 x float>, <32 x float>* %a + %op2 = load <32 x float>, <32 x float>* %b + %res = call <32 x float> @llvm.maximum.v32f32(<32 x float> %op1, <32 x float> %op2) + store <32 x float> %res, <32 x float>* %a + ret void +} + +define void @fmax_v64f32(<64 x float>* %a, <64 x float>* %b) #0 { +; CHECK-LABEL: fmax_v64f32: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64 +; VBITS_GE_2048-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_2048-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] +; VBITS_GE_2048-NEXT: fmax [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s +; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op1 = load <64 x float>, <64 x float>* %a + %op2 = load <64 x float>, <64 x float>* %b + %res = call <64 x float> @llvm.maximum.v64f32(<64 x float> %op1, <64 x float> %op2) + store <64 x float> %res, <64 x float>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) #0 { +; CHECK-LABEL: fmax_v1f64: +; CHECK: fmax d0, d0, d1 +; CHECK-NEXT: ret + %res = call <1 x double> @llvm.maximum.v1f64(<1 x double> %op1, <1 x double> %op2) + ret <1 x double> %res +} + +; Don't use SVE for 128-bit vectors. +define <2 x double> @fmax_v2f64(<2 x double> %op1, <2 x double> %op2) #0 { +; CHECK-LABEL: fmax_v2f64: +; CHECK: fmax v0.2d, v0.2d, v1.2d +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.maximum.v2f64(<2 x double> %op1, <2 x double> %op2) + ret <2 x double> %res +} + +define void @fmax_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { +; CHECK-LABEL: fmax_v4f64: +; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 +; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] +; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] +; CHECK-NEXT: fmax [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d +; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; CHECK-NEXT: ret + %op1 = load <4 x double>, <4 x double>* %a + %op2 = load <4 x double>, <4 x double>* %b + %res = call <4 x double> @llvm.maximum.v4f64(<4 x double> %op1, <4 x double> %op2) + store <4 x double> %res, <4 x double>* %a + ret void +} + +define void @fmax_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +; CHECK-LABEL: fmax_v8f64: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8 +; VBITS_GE_512-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_512-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] +; VBITS_GE_512-NEXT: fmax [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d +; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: add x[[B_HI:[0-9]+]], x1, #32 +; VBITS_EQ_256-DAG: ld1d { [[OP1_LO:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1d { [[OP1_HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: ld1d { [[OP2_LO:z[0-9]+]].d }, [[PG]]/z, [x1] +; VBITS_EQ_256-DAG: ld1d { [[OP2_HI:z[0-9]+]].d }, [[PG]]/z, [x[[B_HI]]] +; VBITS_EQ_256-DAG: fmax [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[OP1_LO]].d, [[OP2_LO]].d +; VBITS_EQ_256-DAG: fmax [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[OP1_HI]].d, [[OP2_HI]].d +; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op1 = load <8 x double>, <8 x double>* %a + %op2 = load <8 x double>, <8 x double>* %b + %res = call <8 x double> @llvm.maximum.v8f64(<8 x double> %op1, <8 x double> %op2) + store <8 x double> %res, <8 x double>* %a + ret void +} + +define void @fmax_v16f64(<16 x double>* %a, <16 x double>* %b) #0 { +; CHECK-LABEL: fmax_v16f64: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16 +; VBITS_GE_1024-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_1024-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] +; VBITS_GE_1024-NEXT: fmax [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d +; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op1 = load <16 x double>, <16 x double>* %a + %op2 = load <16 x double>, <16 x double>* %b + %res = call <16 x double> @llvm.maximum.v16f64(<16 x double> %op1, <16 x double> %op2) + store <16 x double> %res, <16 x double>* %a + ret void +} + +define void @fmax_v32f64(<32 x double>* %a, <32 x double>* %b) #0 { +; CHECK-LABEL: fmax_v32f64: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32 +; VBITS_GE_2048-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_2048-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] +; VBITS_GE_2048-NEXT: fmax [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d +; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op1 = load <32 x double>, <32 x double>* %a + %op2 = load <32 x double>, <32 x double>* %b + %res = call <32 x double> @llvm.maximum.v32f64(<32 x double> %op1, <32 x double> %op2) + store <32 x double> %res, <32 x double>* %a + ret void +} + +; +; FMIN +; + +; Don't use SVE for 64-bit vectors. +define <4 x half> @fmin_v4f16(<4 x half> %op1, <4 x half> %op2) #0 { +; CHECK-LABEL: fmin_v4f16: +; CHECK: fmin v0.4h, v0.4h, v1.4h +; CHECK-NEXT: ret + %res = call <4 x half> @llvm.minimum.v4f16(<4 x half> %op1, <4 x half> %op2) + ret <4 x half> %res +} + +; Don't use SVE for 128-bit vectors. +define <8 x half> @fmin_v8f16(<8 x half> %op1, <8 x half> %op2) #0 { +; CHECK-LABEL: fmin_v8f16: +; CHECK: fmin v0.8h, v0.8h, v1.8h +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.minimum.v8f16(<8 x half> %op1, <8 x half> %op2) + ret <8 x half> %res +} + +define void @fmin_v16f16(<16 x half>* %a, <16 x half>* %b) #0 { +; CHECK-LABEL: fmin_v16f16: +; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 +; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] +; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] +; CHECK-NEXT: fmin [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h +; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; CHECK-NEXT: ret + %op1 = load <16 x half>, <16 x half>* %a + %op2 = load <16 x half>, <16 x half>* %b + %res = call <16 x half> @llvm.minimum.v16f16(<16 x half> %op1, <16 x half> %op2) + store <16 x half> %res, <16 x half>* %a + ret void +} + +define void @fmin_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { +; CHECK-LABEL: fmin_v32f16: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 +; VBITS_GE_512-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_512-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] +; VBITS_GE_512-NEXT: fmin [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h +; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: add x[[B_HI:[0-9]+]], x1, #32 +; VBITS_EQ_256-DAG: ld1h { [[OP1_LO:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1h { [[OP1_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: ld1h { [[OP2_LO:z[0-9]+]].h }, [[PG]]/z, [x1] +; VBITS_EQ_256-DAG: ld1h { [[OP2_HI:z[0-9]+]].h }, [[PG]]/z, [x[[B_HI]]] +; VBITS_EQ_256-DAG: fmin [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[OP1_LO]].h, [[OP2_LO]].h +; VBITS_EQ_256-DAG: fmin [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[OP1_HI]].h, [[OP2_HI]].h +; VBITS_EQ_256-DAG: st1h { [[RES_LO]].h }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1h { [[RES_HI]].h }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op1 = load <32 x half>, <32 x half>* %a + %op2 = load <32 x half>, <32 x half>* %b + %res = call <32 x half> @llvm.minimum.v32f16(<32 x half> %op1, <32 x half> %op2) + store <32 x half> %res, <32 x half>* %a + ret void +} + +define void @fmin_v64f16(<64 x half>* %a, <64 x half>* %b) #0 { +; CHECK-LABEL: fmin_v64f16: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 +; VBITS_GE_1024-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_1024-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] +; VBITS_GE_1024-NEXT: fmin [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h +; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op1 = load <64 x half>, <64 x half>* %a + %op2 = load <64 x half>, <64 x half>* %b + %res = call <64 x half> @llvm.minimum.v64f16(<64 x half> %op1, <64 x half> %op2) + store <64 x half> %res, <64 x half>* %a + ret void +} + +define void @fmin_v128f16(<128 x half>* %a, <128 x half>* %b) #0 { +; CHECK-LABEL: fmin_v128f16: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 +; VBITS_GE_2048-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_2048-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] +; VBITS_GE_2048-NEXT: fmin [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h +; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op1 = load <128 x half>, <128 x half>* %a + %op2 = load <128 x half>, <128 x half>* %b + %res = call <128 x half> @llvm.minimum.v128f16(<128 x half> %op1, <128 x half> %op2) + store <128 x half> %res, <128 x half>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <2 x float> @fmin_v2f32(<2 x float> %op1, <2 x float> %op2) #0 { +; CHECK-LABEL: fmin_v2f32: +; CHECK: fmin v0.2s, v0.2s, v1.2s +; CHECK-NEXT: ret + %res = call <2 x float> @llvm.minimum.v2f32(<2 x float> %op1, <2 x float> %op2) + ret <2 x float> %res +} + +; Don't use SVE for 128-bit vectors. +define <4 x float> @fmin_v4f32(<4 x float> %op1, <4 x float> %op2) #0 { +; CHECK-LABEL: fmin_v4f32: +; CHECK: fmin v0.4s, v0.4s, v1.4s +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.minimum.v4f32(<4 x float> %op1, <4 x float> %op2) + ret <4 x float> %res +} + +define void @fmin_v8f32(<8 x float>* %a, <8 x float>* %b) #0 { +; CHECK-LABEL: fmin_v8f32: +; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 +; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] +; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] +; CHECK-NEXT: fmin [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s +; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; CHECK-NEXT: ret + %op1 = load <8 x float>, <8 x float>* %a + %op2 = load <8 x float>, <8 x float>* %b + %res = call <8 x float> @llvm.minimum.v8f32(<8 x float> %op1, <8 x float> %op2) + store <8 x float> %res, <8 x float>* %a + ret void +} + +define void @fmin_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { +; CHECK-LABEL: fmin_v16f32: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 +; VBITS_GE_512-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_512-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] +; VBITS_GE_512-NEXT: fmin [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s +; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: add x[[B_HI:[0-9]+]], x1, #32 +; VBITS_EQ_256-DAG: ld1w { [[OP1_LO:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1w { [[OP1_HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: ld1w { [[OP2_LO:z[0-9]+]].s }, [[PG]]/z, [x1] +; VBITS_EQ_256-DAG: ld1w { [[OP2_HI:z[0-9]+]].s }, [[PG]]/z, [x[[B_HI]]] +; VBITS_EQ_256-DAG: fmin [[RES_LO:z[0-9]+]].s, [[PG]]/m, [[OP1_LO]].s, [[OP2_LO]].s +; VBITS_EQ_256-DAG: fmin [[RES_HI:z[0-9]+]].s, [[PG]]/m, [[OP1_HI]].s, [[OP2_HI]].s +; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op1 = load <16 x float>, <16 x float>* %a + %op2 = load <16 x float>, <16 x float>* %b + %res = call <16 x float> @llvm.minimum.v16f32(<16 x float> %op1, <16 x float> %op2) + store <16 x float> %res, <16 x float>* %a + ret void +} + +define void @fmin_v32f32(<32 x float>* %a, <32 x float>* %b) #0 { +; CHECK-LABEL: fmin_v32f32: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32 +; VBITS_GE_1024-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_1024-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] +; VBITS_GE_1024-NEXT: fmin [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s +; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op1 = load <32 x float>, <32 x float>* %a + %op2 = load <32 x float>, <32 x float>* %b + %res = call <32 x float> @llvm.minimum.v32f32(<32 x float> %op1, <32 x float> %op2) + store <32 x float> %res, <32 x float>* %a + ret void +} + +define void @fmin_v64f32(<64 x float>* %a, <64 x float>* %b) #0 { +; CHECK-LABEL: fmin_v64f32: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64 +; VBITS_GE_2048-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_2048-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] +; VBITS_GE_2048-NEXT: fmin [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s +; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op1 = load <64 x float>, <64 x float>* %a + %op2 = load <64 x float>, <64 x float>* %b + %res = call <64 x float> @llvm.minimum.v64f32(<64 x float> %op1, <64 x float> %op2) + store <64 x float> %res, <64 x float>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) #0 { +; CHECK-LABEL: fmin_v1f64: +; CHECK: fmin d0, d0, d1 +; CHECK-NEXT: ret + %res = call <1 x double> @llvm.minimum.v1f64(<1 x double> %op1, <1 x double> %op2) + ret <1 x double> %res +} + +; Don't use SVE for 128-bit vectors. +define <2 x double> @fmin_v2f64(<2 x double> %op1, <2 x double> %op2) #0 { +; CHECK-LABEL: fmin_v2f64: +; CHECK: fmin v0.2d, v0.2d, v1.2d +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.minimum.v2f64(<2 x double> %op1, <2 x double> %op2) + ret <2 x double> %res +} + +define void @fmin_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { +; CHECK-LABEL: fmin_v4f64: +; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 +; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] +; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] +; CHECK-NEXT: fmin [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d +; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; CHECK-NEXT: ret + %op1 = load <4 x double>, <4 x double>* %a + %op2 = load <4 x double>, <4 x double>* %b + %res = call <4 x double> @llvm.minimum.v4f64(<4 x double> %op1, <4 x double> %op2) + store <4 x double> %res, <4 x double>* %a + ret void +} + +define void @fmin_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { +; CHECK-LABEL: fmin_v8f64: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8 +; VBITS_GE_512-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_512-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] +; VBITS_GE_512-NEXT: fmin [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d +; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: add x[[B_HI:[0-9]+]], x1, #32 +; VBITS_EQ_256-DAG: ld1d { [[OP1_LO:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1d { [[OP1_HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: ld1d { [[OP2_LO:z[0-9]+]].d }, [[PG]]/z, [x1] +; VBITS_EQ_256-DAG: ld1d { [[OP2_HI:z[0-9]+]].d }, [[PG]]/z, [x[[B_HI]]] +; VBITS_EQ_256-DAG: fmin [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[OP1_LO]].d, [[OP2_LO]].d +; VBITS_EQ_256-DAG: fmin [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[OP1_HI]].d, [[OP2_HI]].d +; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op1 = load <8 x double>, <8 x double>* %a + %op2 = load <8 x double>, <8 x double>* %b + %res = call <8 x double> @llvm.minimum.v8f64(<8 x double> %op1, <8 x double> %op2) + store <8 x double> %res, <8 x double>* %a + ret void +} + +define void @fmin_v16f64(<16 x double>* %a, <16 x double>* %b) #0 { +; CHECK-LABEL: fmin_v16f64: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16 +; VBITS_GE_1024-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_1024-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] +; VBITS_GE_1024-NEXT: fmin [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d +; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op1 = load <16 x double>, <16 x double>* %a + %op2 = load <16 x double>, <16 x double>* %b + %res = call <16 x double> @llvm.minimum.v16f64(<16 x double> %op1, <16 x double> %op2) + store <16 x double> %res, <16 x double>* %a + ret void +} + +define void @fmin_v32f64(<32 x double>* %a, <32 x double>* %b) #0 { +; CHECK-LABEL: fmin_v32f64: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32 +; VBITS_GE_2048-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_2048-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] +; VBITS_GE_2048-NEXT: fmin [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d +; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op1 = load <32 x double>, <32 x double>* %a + %op2 = load <32 x double>, <32 x double>* %b + %res = call <32 x double> @llvm.minimum.v32f64(<32 x double> %op1, <32 x double> %op2) + store <32 x double> %res, <32 x double>* %a + ret void +} + attributes #0 = { "target-features"="+sve" } declare <4 x half> @llvm.minnum.v4f16(<4 x half>, <4 x half>) @@ -619,3 +1179,41 @@ declare <8 x double> @llvm.maxnum.v8f64(<8 x double>, <8 x double>) declare <16 x double> @llvm.maxnum.v16f64(<16 x double>, <16 x double>) declare <32 x double> @llvm.maxnum.v32f64(<32 x double>, <32 x double>) + +declare <4 x half> @llvm.minimum.v4f16(<4 x half>, <4 x half>) +declare <8 x half> @llvm.minimum.v8f16(<8 x half>, <8 x half>) +declare <16 x half> @llvm.minimum.v16f16(<16 x half>, <16 x half>) +declare <32 x half> @llvm.minimum.v32f16(<32 x half>, <32 x half>) +declare <64 x half> @llvm.minimum.v64f16(<64 x half>, <64 x half>) +declare <128 x half> @llvm.minimum.v128f16(<128 x half>, <128 x half>) +declare <2 x float> @llvm.minimum.v2f32(<2 x float>, <2 x float>) +declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>) +declare <8 x float> @llvm.minimum.v8f32(<8 x float>, <8 x float>) +declare <16 x float> @llvm.minimum.v16f32(<16 x float>, <16 x float>) +declare <32 x float> @llvm.minimum.v32f32(<32 x float>, <32 x float>) +declare <64 x float> @llvm.minimum.v64f32(<64 x float>, <64 x float>) +declare <1 x double> @llvm.minimum.v1f64(<1 x double>, <1 x double>) +declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>) +declare <4 x double> @llvm.minimum.v4f64(<4 x double>, <4 x double>) +declare <8 x double> @llvm.minimum.v8f64(<8 x double>, <8 x double>) +declare <16 x double> @llvm.minimum.v16f64(<16 x double>, <16 x double>) +declare <32 x double> @llvm.minimum.v32f64(<32 x double>, <32 x double>) + +declare <4 x half> @llvm.maximum.v4f16(<4 x half>, <4 x half>) +declare <8 x half> @llvm.maximum.v8f16(<8 x half>, <8 x half>) +declare <16 x half> @llvm.maximum.v16f16(<16 x half>, <16 x half>) +declare <32 x half> @llvm.maximum.v32f16(<32 x half>, <32 x half>) +declare <64 x half> @llvm.maximum.v64f16(<64 x half>, <64 x half>) +declare <128 x half> @llvm.maximum.v128f16(<128 x half>, <128 x half>) +declare <2 x float> @llvm.maximum.v2f32(<2 x float>, <2 x float>) +declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>) +declare <8 x float> @llvm.maximum.v8f32(<8 x float>, <8 x float>) +declare <16 x float> @llvm.maximum.v16f32(<16 x float>, <16 x float>) +declare <32 x float> @llvm.maximum.v32f32(<32 x float>, <32 x float>) +declare <64 x float> @llvm.maximum.v64f32(<64 x float>, <64 x float>) +declare <1 x double> @llvm.maximum.v1f64(<1 x double>, <1 x double>) +declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>) +declare <4 x double> @llvm.maximum.v4f64(<4 x double>, <4 x double>) +declare <8 x double> @llvm.maximum.v8f64(<8 x double>, <8 x double>) +declare <16 x double> @llvm.maximum.v16f64(<16 x double>, <16 x double>) +declare <32 x double> @llvm.maximum.v32f64(<32 x double>, <32 x double>) diff --git a/llvm/test/CodeGen/AArch64/sve-fp.ll b/llvm/test/CodeGen/AArch64/sve-fp.ll --- a/llvm/test/CodeGen/AArch64/sve-fp.ll +++ b/llvm/test/CodeGen/AArch64/sve-fp.ll @@ -773,6 +773,194 @@ ret %res } +; maximum minimum + +define @maximum_nxv16f16( %a, %b) { +; CHECK-LABEL: maximum_nxv16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z2.h +; CHECK-NEXT: fmax z1.h, p0/m, z1.h, z3.h +; CHECK-NEXT: ret + %res = call @llvm.maximum.nxv16f16( %a, %b) + ret %res +} + +define @maximum_nxv8f16( %a, %b) { +; CHECK-LABEL: maximum_nxv8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.maximum.nxv8f16( %a, %b) + ret %res +} + +define @maximum_nxv4f16( %a, %b) { +; CHECK-LABEL: maximum_nxv4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.maximum.nxv4f16( %a, %b) + ret %res +} + +define @maximum_nxv2f16( %a, %b) { +; CHECK-LABEL: maximum_nxv2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.maximum.nxv2f16( %a, %b) + ret %res +} + +define @maximum_nxv8f32( %a, %b) { +; CHECK-LABEL: maximum_nxv8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z2.s +; CHECK-NEXT: fmax z1.s, p0/m, z1.s, z3.s +; CHECK-NEXT: ret + %res = call @llvm.maximum.nxv8f32( %a, %b) + ret %res +} + +define @maximum_nxv4f32( %a, %b) { +; CHECK-LABEL: maximum_nxv4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.maximum.nxv4f32( %a, %b) + ret %res +} + +define @maximum_nxv2f32( %a, %b) { +; CHECK-LABEL: maximum_nxv2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.maximum.nxv2f32( %a, %b) + ret %res +} + +define @maximum_nxv4f64( %a, %b) { +; CHECK-LABEL: maximum_nxv4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: fmax z1.d, p0/m, z1.d, z3.d +; CHECK-NEXT: ret + %res = call @llvm.maximum.nxv4f64( %a, %b) + ret %res +} + +define @maximum_nxv2f64( %a, %b) { +; CHECK-LABEL: maximum_nxv2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.maximum.nxv2f64( %a, %b) + ret %res +} + +define @minimum_nxv16f16( %a, %b) { +; CHECK-LABEL: minimum_nxv16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z2.h +; CHECK-NEXT: fmin z1.h, p0/m, z1.h, z3.h +; CHECK-NEXT: ret + %res = call @llvm.minimum.nxv16f16( %a, %b) + ret %res +} + +define @minimum_nxv8f16( %a, %b) { +; CHECK-LABEL: minimum_nxv8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.minimum.nxv8f16( %a, %b) + ret %res +} + +define @minimum_nxv4f16( %a, %b) { +; CHECK-LABEL: minimum_nxv4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.minimum.nxv4f16( %a, %b) + ret %res +} + +define @minimum_nxv2f16( %a, %b) { +; CHECK-LABEL: minimum_nxv2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.minimum.nxv2f16( %a, %b) + ret %res +} + +define @minimum_nxv8f32( %a, %b) { +; CHECK-LABEL: minimum_nxv8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z2.s +; CHECK-NEXT: fmin z1.s, p0/m, z1.s, z3.s +; CHECK-NEXT: ret + %res = call @llvm.minimum.nxv8f32( %a, %b) + ret %res +} + +define @minimum_nxv4f32( %a, %b) { +; CHECK-LABEL: minimum_nxv4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.minimum.nxv4f32( %a, %b) + ret %res +} + +define @minimum_nxv2f32( %a, %b) { +; CHECK-LABEL: minimum_nxv2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.minimum.nxv2f32( %a, %b) + ret %res +} + +define @minimum_nxv4f64( %a, %b) { +; CHECK-LABEL: minimum_nxv4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: fmin z1.d, p0/m, z1.d, z3.d +; CHECK-NEXT: ret + %res = call @llvm.minimum.nxv4f64( %a, %b) + ret %res +} + +define @minimum_nxv2f64( %a, %b) { +; CHECK-LABEL: minimum_nxv2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.minimum.nxv2f64( %a, %b) + ret %res +} + declare @llvm.aarch64.sve.frecps.x.nxv8f16(, ) declare @llvm.aarch64.sve.frecps.x.nxv4f32( , ) declare @llvm.aarch64.sve.frecps.x.nxv2f64(, ) @@ -821,5 +1009,24 @@ declare @llvm.minnum.nxv4f64(, ) declare @llvm.minnum.nxv2f64(, ) +declare @llvm.maximum.nxv16f16(, ) +declare @llvm.maximum.nxv8f16(, ) +declare @llvm.maximum.nxv4f16(, ) +declare @llvm.maximum.nxv2f16(, ) +declare @llvm.maximum.nxv8f32(, ) +declare @llvm.maximum.nxv4f32(, ) +declare @llvm.maximum.nxv2f32(, ) +declare @llvm.maximum.nxv4f64(, ) +declare @llvm.maximum.nxv2f64(, ) +declare @llvm.minimum.nxv16f16(, ) +declare @llvm.minimum.nxv8f16(, ) +declare @llvm.minimum.nxv4f16(, ) +declare @llvm.minimum.nxv2f16(, ) +declare @llvm.minimum.nxv8f32(, ) +declare @llvm.minimum.nxv4f32(, ) +declare @llvm.minimum.nxv2f32(, ) +declare @llvm.minimum.nxv4f64(, ) +declare @llvm.minimum.nxv2f64(, ) + ; Function Attrs: nounwind readnone declare double @llvm.aarch64.sve.faddv.nxv2f64(, ) #2