diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp --- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp @@ -90,6 +90,18 @@ Block &MBB, BlockIt MBBI); + /// Specific shift implementation. + bool expandLSLB7Rd(Block &MBB, BlockIt MBBI); + bool expandLSRB7Rd(Block &MBB, BlockIt MBBI); + bool expandASRB7Rd(Block &MBB, BlockIt MBBI); + bool expandLSLW4Rd(Block &MBB, BlockIt MBBI); + bool expandLSRW4Rd(Block &MBB, BlockIt MBBI); + bool expandLSLW8Rd(Block &MBB, BlockIt MBBI); + bool expandLSRW8Rd(Block &MBB, BlockIt MBBI); + bool expandASRW8Rd(Block &MBB, BlockIt MBBI); + bool expandLSLW12Rd(Block &MBB, BlockIt MBBI); + bool expandLSRW12Rd(Block &MBB, BlockIt MBBI); + /// Scavenges a free GPR8 register for use. Register scavengeGPR8(MachineInstr &MI); }; @@ -1403,14 +1415,13 @@ return true; } -template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expandLSLW4Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstLoReg, DstHiReg; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); TRI->splitReg(DstReg, DstLoReg, DstHiReg); // swap Rh @@ -1462,14 +1473,13 @@ return true; } -template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expandLSLW8Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstLoReg, DstHiReg; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); TRI->splitReg(DstReg, DstLoReg, DstHiReg); // mov Rh, Rl @@ -1490,14 +1500,13 @@ return true; } -template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstLoReg, DstHiReg; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); TRI->splitReg(DstReg, DstLoReg, DstHiReg); // mov Rh, Rl @@ -1532,6 +1541,23 @@ return true; } +template <> +bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { + MachineInstr &MI = *MBBI; + unsigned Imm = MI.getOperand(2).getImm(); + switch (Imm) { + case 4: + return expandLSLW4Rd(MBB, MBBI); + case 8: + return expandLSLW8Rd(MBB, MBBI); + case 12: + return expandLSLW12Rd(MBB, MBBI); + default: + llvm_unreachable("unimplemented lslwn"); + return false; + } +} + template <> bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; @@ -1563,14 +1589,13 @@ return true; } -template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expandLSRW4Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstLoReg, DstHiReg; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); TRI->splitReg(DstReg, DstLoReg, DstHiReg); // swap Rh @@ -1622,14 +1647,13 @@ return true; } -template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expandLSRW8Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstLoReg, DstHiReg; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); TRI->splitReg(DstReg, DstLoReg, DstHiReg); // Move upper byte to lower byte. @@ -1650,14 +1674,13 @@ return true; } -template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expandLSRW12Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstLoReg, DstHiReg; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); TRI->splitReg(DstReg, DstLoReg, DstHiReg); // Move upper byte to lower byte. @@ -1692,6 +1715,23 @@ return true; } +template <> +bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { + MachineInstr &MI = *MBBI; + unsigned Imm = MI.getOperand(2).getImm(); + switch (Imm) { + case 4: + return expandLSRW4Rd(MBB, MBBI); + case 8: + return expandLSRW8Rd(MBB, MBBI); + case 12: + return expandLSRW12Rd(MBB, MBBI); + default: + llvm_unreachable("unimplemented lsrwn"); + return false; + } +} + template <> bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { llvm_unreachable("RORW unimplemented"); @@ -1735,14 +1775,13 @@ return true; } -template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expandASRW8Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstLoReg, DstHiReg; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); TRI->splitReg(DstReg, DstLoReg, DstHiReg); // Move upper byte to lower byte. @@ -1770,12 +1809,24 @@ } template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { + MachineInstr &MI = *MBBI; + unsigned Imm = MI.getOperand(2).getImm(); + switch (Imm) { + case 8: + return expandASRW8Rd(MBB, MBBI); + default: + llvm_unreachable("unimplemented asrwn"); + return false; + } +} + +bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); // ror r24 // clr r24 @@ -1807,12 +1858,24 @@ } template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { + MachineInstr &MI = *MBBI; + unsigned Imm = MI.getOperand(2).getImm(); + switch (Imm) { + case 7: + return expandLSLB7Rd(MBB, MBBI); + default: + llvm_unreachable("unimplemented lslbn"); + return false; + } +} + +bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); // rol r24 // clr r24 @@ -1846,12 +1909,24 @@ } template <> -bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { +bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { + MachineInstr &MI = *MBBI; + unsigned Imm = MI.getOperand(2).getImm(); + switch (Imm) { + case 7: + return expandLSRB7Rd(MBB, MBBI); + default: + llvm_unreachable("unimplemented lsrbn"); + return false; + } +} + +bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); - bool ImpIsDead = MI.getOperand(2).isDead(); + bool ImpIsDead = MI.getOperand(3).isDead(); // lsl r24 // sbc r24, r24 @@ -1876,6 +1951,19 @@ return true; } +template <> +bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { + MachineInstr &MI = *MBBI; + unsigned Imm = MI.getOperand(2).getImm(); + switch (Imm) { + case 7: + return expandASRB7Rd(MBB, MBBI); + default: + llvm_unreachable("unimplemented asrbn"); + return false; + } +} + template <> bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { MachineInstr &MI = *MBBI; Register DstLoReg, DstHiReg; @@ -2093,20 +2181,16 @@ EXPAND(AVR::ROLBRd); EXPAND(AVR::RORBRd); EXPAND(AVR::LSLWRd); - EXPAND(AVR::LSLW4Rd); - EXPAND(AVR::LSLW8Rd); - EXPAND(AVR::LSLW12Rd); EXPAND(AVR::LSRWRd); - EXPAND(AVR::LSRW4Rd); - EXPAND(AVR::LSRW8Rd); - EXPAND(AVR::LSRW12Rd); EXPAND(AVR::RORWRd); EXPAND(AVR::ROLWRd); EXPAND(AVR::ASRWRd); - EXPAND(AVR::ASRW8Rd); - EXPAND(AVR::LSLB7Rd); - EXPAND(AVR::LSRB7Rd); - EXPAND(AVR::ASRB7Rd); + EXPAND(AVR::LSLWNRd); + EXPAND(AVR::LSRWNRd); + EXPAND(AVR::ASRWNRd); + EXPAND(AVR::LSLBNRd); + EXPAND(AVR::LSRBNRd); + EXPAND(AVR::ASRBNRd); EXPAND(AVR::SEXT); EXPAND(AVR::ZEXT); EXPAND(AVR::SPREAD); diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h --- a/llvm/lib/Target/AVR/AVRISelLowering.h +++ b/llvm/lib/Target/AVR/AVRISelLowering.h @@ -36,18 +36,14 @@ /// TargetExternalSymbol, and TargetGlobalAddress. WRAPPER, LSL, ///< Logical shift left. - LSL4, ///< Logical shift left 4 bits. - LSL8, ///< Logical shift left 8 bits. - LSL12, ///< Logical shift left 12 bits. + LSLBN, ///< Byte logical shift left N bits. + LSLWN, ///< Word logical shift left N bits. LSR, ///< Logical shift right. - LSR4, ///< Logical shift right 4 bits. - LSR8, ///< Logical shift right 8 bits. - LSR12, ///< Logical shift right 12 bits. + LSRBN, ///< Byte logical shift right N bits. + LSRWN, ///< Word logical shift right N bits. ASR, ///< Arithmetic shift right. - ASR8, ///< Arithmetic shift right 8 bits. - LSL7, ///< Logical shift left 7 bits. - LSR7, ///< Logical shift right 7 bits. - ASR7, ///< Arithmetic shift right 7 bits. + ASRBN, ///< Byte arithmetic shift right N bits. + ASRWN, ///< Word arithmetic shift right N bits. ROR, ///< Bit rotate right. ROL, ///< Bit rotate left. LSLLOOP, ///< A loop of single logical shift left instructions. diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -351,26 +351,31 @@ ShiftAmount -= 4; } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) { // Optimize LSL when ShiftAmount == 7. - Victim = DAG.getNode(AVRISD::LSL7, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim, + DAG.getConstant(7, dl, VT)); ShiftAmount = 0; } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { // Optimize LSR when ShiftAmount == 7. - Victim = DAG.getNode(AVRISD::LSR7, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim, + DAG.getConstant(7, dl, VT)); ShiftAmount = 0; } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { // Optimize ASR when ShiftAmount == 7. - Victim = DAG.getNode(AVRISD::ASR7, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, + DAG.getConstant(7, dl, VT)); ShiftAmount = 0; } } else if (VT.getSizeInBits() == 16) { if (4 <= ShiftAmount && ShiftAmount < 8) switch (Op.getOpcode()) { case ISD::SHL: - Victim = DAG.getNode(AVRISD::LSL4, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, + DAG.getConstant(4, dl, VT)); ShiftAmount -= 4; break; case ISD::SRL: - Victim = DAG.getNode(AVRISD::LSR4, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, + DAG.getConstant(4, dl, VT)); ShiftAmount -= 4; break; default: @@ -379,15 +384,18 @@ else if (8 <= ShiftAmount && ShiftAmount < 12) switch (Op.getOpcode()) { case ISD::SHL: - Victim = DAG.getNode(AVRISD::LSL8, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, + DAG.getConstant(8, dl, VT)); ShiftAmount -= 8; break; case ISD::SRL: - Victim = DAG.getNode(AVRISD::LSR8, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, + DAG.getConstant(8, dl, VT)); ShiftAmount -= 8; break; case ISD::SRA: - Victim = DAG.getNode(AVRISD::ASR8, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, + DAG.getConstant(8, dl, VT)); ShiftAmount -= 8; break; default: @@ -396,11 +404,13 @@ else if (12 <= ShiftAmount) switch (Op.getOpcode()) { case ISD::SHL: - Victim = DAG.getNode(AVRISD::LSL12, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, + DAG.getConstant(12, dl, VT)); ShiftAmount -= 12; break; case ISD::SRL: - Victim = DAG.getNode(AVRISD::LSR12, dl, VT, Victim); + Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, + DAG.getConstant(12, dl, VT)); ShiftAmount -= 12; break; default: diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td --- a/llvm/lib/Target/AVR/AVRInstrInfo.td +++ b/llvm/lib/Target/AVR/AVRInstrInfo.td @@ -55,20 +55,16 @@ // Shift nodes. def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>; -def AVRlsl4 : SDNode<"AVRISD::LSL4", SDTIntUnaryOp>; -def AVRlsl8 : SDNode<"AVRISD::LSL8", SDTIntUnaryOp>; -def AVRlsl12 : SDNode<"AVRISD::LSL12", SDTIntUnaryOp>; def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>; -def AVRlsr4 : SDNode<"AVRISD::LSR4", SDTIntUnaryOp>; -def AVRlsr8 : SDNode<"AVRISD::LSR8", SDTIntUnaryOp>; -def AVRlsr12 : SDNode<"AVRISD::LSR12", SDTIntUnaryOp>; def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>; def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>; def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>; -def AVRasr8 : SDNode<"AVRISD::ASR8", SDTIntUnaryOp>; -def AVRlsl7 : SDNode<"AVRISD::LSL7", SDTIntUnaryOp>; -def AVRlsr7 : SDNode<"AVRISD::LSR7", SDTIntUnaryOp>; -def AVRasr7 : SDNode<"AVRISD::ASR7", SDTIntUnaryOp>; +def AVRlslbn : SDNode<"AVRISD::LSLBN", SDTIntBinOp>; +def AVRlsrbn : SDNode<"AVRISD::LSRBN", SDTIntBinOp>; +def AVRasrbn : SDNode<"AVRISD::ASRBN", SDTIntBinOp>; +def AVRlslwn : SDNode<"AVRISD::LSLWN", SDTIntBinOp>; +def AVRlsrwn : SDNode<"AVRISD::LSRWN", SDTIntBinOp>; +def AVRasrwn : SDNode<"AVRISD::ASRWN", SDTIntBinOp>; // Pseudo shift nodes for non-constant shift amounts. def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>; @@ -1676,25 +1672,17 @@ "lslw\t$rd", [(set i16:$rd, (AVRlsl i16:$src)), (implicit SREG)]>; - def LSLB7Rd : Pseudo<(outs GPR8:$rd), - (ins GPR8:$src), - "lslb7\t$rd", - [(set i8:$rd, (AVRlsl7 i8:$src)), (implicit SREG)]>; - - def LSLW4Rd : Pseudo<(outs DLDREGS:$rd), - (ins DREGS:$src), - "lslw4\t$rd", - [(set i16:$rd, (AVRlsl4 i16:$src)), (implicit SREG)]>; - - def LSLW8Rd : Pseudo<(outs DREGS:$rd), - (ins DREGS:$src), - "lslw8\t$rd", - [(set i16:$rd, (AVRlsl8 i16:$src)), (implicit SREG)]>; + def LSLWNRd : Pseudo<(outs DLDREGS:$rd), + (ins DREGS:$src, imm16:$bits), + "lslwn\t$rd, $bits", + [(set i16:$rd, (AVRlslwn i16:$src, imm:$bits)), + (implicit SREG)]>; - def LSLW12Rd : Pseudo<(outs DLDREGS:$rd), - (ins DREGS:$src), - "lslw12\t$rd", - [(set i16:$rd, (AVRlsl12 i16:$src)), (implicit SREG)]>; + def LSLBNRd : Pseudo<(outs LD8:$rd), + (ins GPR8:$src, imm_ldi8:$bits), + "lslbn\t$rd, $bits", + [(set i8:$rd, (AVRlslbn i8:$src, imm:$bits)), + (implicit SREG)]>; def LSRRd : FRd<0b1001, 0b0100110, @@ -1703,30 +1691,22 @@ "lsr\t$rd", [(set i8:$rd, (AVRlsr i8:$src)), (implicit SREG)]>; - def LSRB7Rd : Pseudo<(outs GPR8:$rd), - (ins GPR8:$src), - "lsrb7\t$rd", - [(set i8:$rd, (AVRlsr7 i8:$src)), (implicit SREG)]>; - def LSRWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "lsrw\t$rd", [(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>; - def LSRW4Rd : Pseudo<(outs DLDREGS:$rd), - (ins DREGS:$src), - "lsrw4\t$rd", - [(set i16:$rd, (AVRlsr4 i16:$src)), (implicit SREG)]>; - - def LSRW8Rd : Pseudo<(outs DREGS:$rd), - (ins DREGS:$src), - "lsrw8\t$rd", - [(set i16:$rd, (AVRlsr8 i16:$src)), (implicit SREG)]>; + def LSRWNRd : Pseudo<(outs DLDREGS:$rd), + (ins DREGS:$src, imm16:$bits), + "lsrwn\t$rd, $bits", + [(set i16:$rd, (AVRlsrwn i16:$src, imm:$bits)), + (implicit SREG)]>; - def LSRW12Rd : Pseudo<(outs DLDREGS:$rd), - (ins DREGS:$src), - "lsrw12\t$rd", - [(set i16:$rd, (AVRlsr12 i16:$src)), (implicit SREG)]>; + def LSRBNRd : Pseudo<(outs LD8:$rd), + (ins GPR8:$src, imm_ldi8:$bits), + "lsrbn\t$rd, $bits", + [(set i8:$rd, (AVRlsrbn i8:$src, imm:$bits)), + (implicit SREG)]>; def ASRRd : FRd<0b1001, 0b0100101, @@ -1735,21 +1715,23 @@ "asr\t$rd", [(set i8:$rd, (AVRasr i8:$src)), (implicit SREG)]>; - def ASRB7Rd : Pseudo<(outs GPR8:$rd), - (ins GPR8:$src), - "asrb7\t$rd", - [(set i8:$rd, (AVRasr7 i8:$src)), (implicit SREG)]>; + def ASRWNRd : Pseudo<(outs DLDREGS:$rd), + (ins DREGS:$src, imm16:$bits), + "asrwn\t$rd, $bits", + [(set i16:$rd, (AVRasrwn i16:$src, imm:$bits)), + (implicit SREG)]>; + + def ASRBNRd : Pseudo<(outs LD8:$rd), + (ins GPR8:$src, imm_ldi8:$bits), + "asrbn\t$rd, $bits", + [(set i8:$rd, (AVRasrbn i8:$src, imm:$bits)), + (implicit SREG)]>; def ASRWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "asrw\t$rd", [(set i16:$rd, (AVRasr i16:$src)), (implicit SREG)]>; - def ASRW8Rd : Pseudo<(outs DREGS:$rd), - (ins DREGS:$src), - "asrw8\t$rd", - [(set i16:$rd, (AVRasr8 i16:$src)), (implicit SREG)]>; - // Bit rotate operations. let Uses = [SREG] in { @@ -2165,7 +2147,7 @@ def : Pat<(i16 (AVRWrapper tblockaddress:$dst)), (LDIWRdK tblockaddress:$dst)>; -def : Pat<(i8 (trunc (AVRlsr8 DREGS:$src))), +def : Pat<(i8 (trunc (AVRlsrwn DLDREGS:$src, (i16 8)))), (EXTRACT_SUBREG DREGS:$src, sub_hi)>; // :FIXME: DAGCombiner produces an shl node after legalization from these seq: