diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -272,6 +272,17 @@
                                                   FeatureStdExtD,
                                                   FeatureStdExtC]>;
 
+def : ProcessorModel<"sifive-viu75", SiFive7Model, [Feature64Bit,
+                                                    FeatureStdExtM,
+                                                    FeatureStdExtA,
+                                                    FeatureStdExtF,
+                                                    FeatureStdExtD,
+                                                    FeatureStdExtC,
+                                                    FeatureStdExtV,
+                                                    FeatureStdExtZvlsseg,
+                                                    FeatureExtZvamo,
+                                                    FeatureExtZfh]>;
+
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.
 //===----------------------------------------------------------------------===//