diff --git a/mlir/include/mlir/Target/LLVMIR.h b/mlir/include/mlir/Target/LLVMIR/Import.h
rename from mlir/include/mlir/Target/LLVMIR.h
rename to mlir/include/mlir/Target/LLVMIR/Import.h
--- a/mlir/include/mlir/Target/LLVMIR.h
+++ b/mlir/include/mlir/Target/LLVMIR/Import.h
@@ -1,4 +1,4 @@
-//===- LLVMIR.h - MLIR to LLVM IR conversion --------------------*- C++ -*-===//
+//===- Import.h - LLVM IR To MLIR translation -------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,12 +6,12 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the entry point for the MLIR to LLVM IR conversion.
+// This file declares the entry point for the LLVM IR to MLIR conversion.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_TARGET_LLVMIR_H
-#define MLIR_TARGET_LLVMIR_H
+#ifndef MLIR_TARGET_LLVMIR_IMPORT_H
+#define MLIR_TARGET_LLVMIR_IMPORT_H
 
 #include "mlir/Support/LLVM.h"
 #include "llvm/ADT/StringRef.h"
@@ -38,4 +38,4 @@
 
 } // namespace mlir
 
-#endif // MLIR_TARGET_LLVMIR_H
+#endif // MLIR_TARGET_LLVMIR_IMPORT_H
diff --git a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
--- a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
+++ b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
@@ -15,7 +15,7 @@
 #include "mlir/IR/BuiltinOps.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/MLIRContext.h"
-#include "mlir/Target/LLVMIR.h"
+#include "mlir/Target/LLVMIR/Import.h"
 #include "mlir/Translation.h"
 
 #include "llvm/ADT/TypeSwitch.h"
diff --git a/mlir/test/Target/arm-neon.mlir b/mlir/test/Target/LLVMIR/arm-neon.mlir
rename from mlir/test/Target/arm-neon.mlir
rename to mlir/test/Target/LLVMIR/arm-neon.mlir
diff --git a/mlir/test/Target/arm-sve.mlir b/mlir/test/Target/LLVMIR/arm-sve.mlir
rename from mlir/test/Target/arm-sve.mlir
rename to mlir/test/Target/LLVMIR/arm-sve.mlir
diff --git a/mlir/test/Target/avx512.mlir b/mlir/test/Target/LLVMIR/avx512.mlir
rename from mlir/test/Target/avx512.mlir
rename to mlir/test/Target/LLVMIR/avx512.mlir
diff --git a/mlir/test/Target/import.ll b/mlir/test/Target/LLVMIR/import.ll
rename from mlir/test/Target/import.ll
rename to mlir/test/Target/LLVMIR/import.ll
diff --git a/mlir/test/Target/llvmir-debug.mlir b/mlir/test/Target/LLVMIR/llvmir-debug.mlir
rename from mlir/test/Target/llvmir-debug.mlir
rename to mlir/test/Target/LLVMIR/llvmir-debug.mlir
diff --git a/mlir/test/Target/llvmir-intrinsics.mlir b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
rename from mlir/test/Target/llvmir-intrinsics.mlir
rename to mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
diff --git a/mlir/test/Target/llvmir-invalid.mlir b/mlir/test/Target/LLVMIR/llvmir-invalid.mlir
rename from mlir/test/Target/llvmir-invalid.mlir
rename to mlir/test/Target/LLVMIR/llvmir-invalid.mlir
diff --git a/mlir/test/Target/llvmir-types.mlir b/mlir/test/Target/LLVMIR/llvmir-types.mlir
rename from mlir/test/Target/llvmir-types.mlir
rename to mlir/test/Target/LLVMIR/llvmir-types.mlir
diff --git a/mlir/test/Target/llvmir.mlir b/mlir/test/Target/LLVMIR/llvmir.mlir
rename from mlir/test/Target/llvmir.mlir
rename to mlir/test/Target/LLVMIR/llvmir.mlir
diff --git a/mlir/test/Target/nvvmir.mlir b/mlir/test/Target/LLVMIR/nvvmir.mlir
rename from mlir/test/Target/nvvmir.mlir
rename to mlir/test/Target/LLVMIR/nvvmir.mlir
diff --git a/mlir/test/Target/openmp-llvm.mlir b/mlir/test/Target/LLVMIR/openmp-llvm.mlir
rename from mlir/test/Target/openmp-llvm.mlir
rename to mlir/test/Target/LLVMIR/openmp-llvm.mlir
diff --git a/mlir/test/Target/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
rename from mlir/test/Target/rocdl.mlir
rename to mlir/test/Target/LLVMIR/rocdl.mlir
diff --git a/mlir/test/Target/vector-to-llvm-ir.mlir b/mlir/test/Target/LLVMIR/vector-to-llvm-ir.mlir
rename from mlir/test/Target/vector-to-llvm-ir.mlir
rename to mlir/test/Target/LLVMIR/vector-to-llvm-ir.mlir