diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -1698,6 +1698,16 @@
                                    Position::AFTER);
     }
 
+    // LLVM IR does not support the nontemporal attribute on atomic operations
+    // so there is no need to handle it.
+
+    // FIXME: Currently LLVM IR marks all atomic operations as volatile. So it
+    // is not possible to tell in LLVM IR if it is a non-volatile atomic, or a
+    // volatile atomic. Treating a non-volatile atomic operation as volatile is
+    // too costly as it would cause it to bypass all caches. So for now we
+    // immediately return and ignore any volatile setting. When LLVM IR is
+    // corrected to record volatile and atomic memory ordering independently,
+    // this code needs to be updated.
     return Changed;
   }
 
@@ -1731,6 +1741,16 @@
                                    MOI.getIsCrossAddressSpaceOrdering(),
                                    Position::BEFORE);
 
+    // LLVM IR does not support the nontemporal attribute on atomic operations
+    // so there is no need to handle it.
+
+    // FIXME: Currently LLVM IR marks all atomic operations as volatile. So it
+    // is not possible to tell in LLVM IR if it is a non-volatile atomic, or a
+    // volatile atomic. Treating a non-volatile atomic operation as volatile is
+    // too costly as it would cause it to bypass all caches. So for now we
+    // immediately return and ignore any volatile setting. When LLVM IR is
+    // corrected to record volatile and atomic memory ordering independently,
+    // this code needs to be updated.
     return Changed;
   }
 
@@ -1826,6 +1846,16 @@
                                    Position::AFTER);
     }
 
+    // LLVM IR does not support the nontemporal attribute on atomic operations
+    // so there is no need to handle it.
+
+    // FIXME: Currently LLVM IR marks all atomic operations as volatile. So it
+    // is not possible to tell in LLVM IR if it is a non-volatile atomic, or a
+    // volatile atomic. Treating a non-volatile atomic operation as volatile is
+    // too costly as it would cause it to bypass all caches. So for now we
+    // immediately return and ignore any volatile setting. When LLVM IR is
+    // corrected to record volatile and atomic memory ordering independently,
+    // this code needs to be updated.
     return Changed;
   }