diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -77,6 +77,39 @@ }]; } +//===----------------------------------------------------------------------===// +// Scheduling definitions. +//===----------------------------------------------------------------------===// + +class VMVRSched: Sched <[!cast("WriteVMov" # n # "V"), + !cast("ReadVMov" # n # "V")]>; + +class VLESched : Sched <[!cast("WriteVLDE" # n), + ReadVLDX, ReadVMask]>; + +class VSESched : Sched <[!cast("WriteVSTE" # n), + !cast("ReadVSTE" # n # "V"), + ReadVSTX, ReadVMask]>; + +class VLSSched : Sched <[!cast("WriteVLDS" # n), + ReadVLDX, ReadVLDSX, ReadVMask]>; + +class VSSSched : Sched <[!cast("WriteVSTS" # n), + !cast("ReadVSTS" # n # "V"), + ReadVSTX, ReadVSTSX, ReadVMask]>; + +class VLXSched : + Sched <[!cast("WriteVLD" # o # "X" # n), + ReadVLDX, !cast("ReadVLD" # o # "XV"), ReadVMask]>; + +class VSXSched : + Sched <[!cast("WriteVST" # o # "X" # n), + !cast("ReadVST" # o # "X" # n), + ReadVSTX, !cast("ReadVST" # o # "XV"), ReadVMask]>; + +class VLFSched : Sched <[!cast("WriteVLDFF" # n), + ReadVLDX, ReadVMask]>; + //===----------------------------------------------------------------------===// // Instruction class templates //===----------------------------------------------------------------------===// @@ -328,106 +361,417 @@ // Use these multiclasses to define instructions more easily. //===----------------------------------------------------------------------===// multiclass VALU_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { - def V : VALUVV; - def X : VALUVX; - def I : VALUVI; + def V : VALUVV, + Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>; } multiclass VALU_IV_V_X funct6, string vw = "v"> { - def V : VALUVV; - def X : VALUVX; + def V : VALUVV, + Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>; } -multiclass VALUr_IV_V_X funct6, string vw = "v"> { - def V : VALUrVV; - def X : VALUrVX; +multiclass VALU_IV_X_I funct6, Operand optype = simm5, string vw = "v"> { + def X : VALUVX, + Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>; } -multiclass VALU_IV_X_I funct6, Operand optype = simm5, string vw = "v"> { - def X : VALUVX; - def I : VALUVI; +multiclass VALU_MV_V_X funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVIWALUV, ReadVIWALUV, ReadVIWALUV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVIWALUX, ReadVIWALUV, ReadVIWALUX, ReadVMask]>; } -multiclass VALU_IV_V funct6> { - def _VS : VALUVV; +multiclass VMAC_MV_V_X funct6, string vw = "v"> { + def V : VALUrVV, + Sched<[WriteVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVMask]>; + def X : VALUrVX, + Sched<[WriteVIMulAddX, ReadVIMulAddV, ReadVIMulAddX, ReadVMask]>; } -multiclass VALUr_IV_X funct6, string vw = "v"> { - def X : VALUrVX; +multiclass VWMAC_MV_V_X funct6, string vw = "v"> { + def V : VALUrVV, + Sched<[WriteVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVMask]>; + def X : VALUrVX, + Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>; } -multiclass VALU_MV_V_X funct6, string vw = "v"> { - def V : VALUVV; - def X : VALUVX; +multiclass VWMAC_MV_X funct6, string vw = "v"> { + def X : VALUrVX, + Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>; +} + +multiclass VALU_MV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVExtV, ReadVExtV, ReadVMask]>; +} + +multiclass VALUm_IV_V_X_I funct6> { + def VM : VALUmVV, + Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>; + def XM : VALUmVX, + Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>; + def IM : VALUmVI, + Sched<[WriteVICALUI, ReadVIALUCV, ReadVMask]>; } -multiclass VALU_MV_V funct6> { - def _VS : VALUVV; +multiclass VMRG_IV_V_X_I funct6> { + def VM : VALUmVV, + Sched<[WriteVIMergeV, ReadVIMergeV, ReadVIMergeV, ReadVMask]>; + def XM : VALUmVX, + Sched<[WriteVIMergeX, ReadVIMergeV, ReadVIMergeX, ReadVMask]>; + def IM : VALUmVI, + Sched<[WriteVIMergeI, ReadVIMergeV, ReadVMask]>; } -multiclass VALU_MV_Mask funct6, string vm = "v"> { - def M : VALUVVNoVm; +multiclass VALUm_IV_V_X funct6> { + def VM : VALUmVV, + Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>; + def XM : VALUmVX, + Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>; } -multiclass VALU_MV_X funct6, string vw = "v"> { - def X : VALUVX; +multiclass VALUNoVm_IV_V_X_I funct6, Operand optype = simm5> { + def V : VALUVVNoVm, + Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>; + def X : VALUVXNoVm, + Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>; + def I : VALUVINoVm, + Sched<[WriteVICALUI, ReadVIALUCV]>; } -multiclass VALUr_MV_V_X funct6, string vw = "v"> { - def V : VALUrVV; - def X : VALUrVX; +multiclass VALUNoVm_IV_V_X funct6> { + def V : VALUVVNoVm, + Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>; + def X : VALUVXNoVm, + Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>; } -multiclass VALUr_MV_X funct6, string vw = "v"> { - def X : VALUrVX; +multiclass VALU_FV_V_F funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVFALUV, ReadVFALUV, ReadVFALUV, ReadVMask]>; + def F : VALUVF, + Sched<[WriteVFALUF, ReadVFALUV, ReadVFALUF, ReadVMask]>; } -multiclass VALU_MV_VS2 funct6, bits<5> vs1> { - def "" : VALUVs2; +multiclass VALU_FV_F funct6, string vw = "v"> { + def F : VALUVF, + Sched<[WriteVFALUF, ReadVFALUV, ReadVFALUF, ReadVMask]>; } -multiclass VALUm_IV_V_X_I funct6> { - def VM : VALUmVV; - def XM : VALUmVX; - def IM : VALUmVI; +multiclass VWALU_FV_V_F funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVFWALUV, ReadVFWALUV, ReadVFWALUV, ReadVMask]>; + def F : VALUVF, + Sched<[WriteVFWALUF, ReadVFWALUV, ReadVFWALUF, ReadVMask]>; } -multiclass VALUm_IV_V_X funct6> { - def VM : VALUmVV; - def XM : VALUmVX; +multiclass VMUL_FV_V_F funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVFMulV, ReadVFMulV, ReadVFMulV, ReadVMask]>; + def F : VALUVF, + Sched<[WriteVFMulF, ReadVFMulV, ReadVFMulF, ReadVMask]>; } -multiclass VALUNoVm_IV_V_X_I funct6, Operand optype = simm5> { - def V : VALUVVNoVm; - def X : VALUVXNoVm; - def I : VALUVINoVm; +multiclass VDIV_FV_V_F funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVFDivV, ReadVFDivV, ReadVFDivV, ReadVMask]>; + def F : VALUVF, + Sched<[WriteVFDivF, ReadVFDivV, ReadVFDivF, ReadVMask]>; } -multiclass VALUNoVm_IV_V_X funct6> { - def V : VALUVVNoVm; - def X : VALUVXNoVm; +multiclass VRDIV_FV_F funct6, string vw = "v"> { + def F : VALUVF, + Sched<[WriteVFDivF, ReadVFDivV, ReadVFDivF, ReadVMask]>; } -multiclass VALU_FV_V_F funct6, string vw = "v"> { - def V : VALUVV; - def F : VALUVF; +multiclass VWMUL_FV_V_F funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVFWMulV, ReadVFWMulV, ReadVFWMulV, ReadVMask]>; + def F : VALUVF, + Sched<[WriteVFWMulF, ReadVFWMulV, ReadVFWMulF, ReadVMask]>; } -multiclass VALU_FV_F funct6, string vw = "v"> { - def F : VALUVF; +multiclass VMAC_FV_V_F funct6, string vw = "v"> { + def V : VALUrVV, + Sched<[WriteVFMulAddV, ReadVFMulAddV, ReadVFMulAddV, ReadVMask]>; + def F : VALUrVF, + Sched<[WriteVFMulAddF, ReadVFMulAddV, ReadVFMulAddF, ReadVMask]>; +} + +multiclass VWMAC_FV_V_F funct6, string vw = "v"> { + def V : VALUrVV, + Sched<[WriteVFWMulAddV, ReadVFWMulAddV, ReadVFWMulAddV, ReadVMask]>; + def F : VALUrVF, + Sched<[WriteVFWMulAddF, ReadVFWMulAddV, ReadVFWMulAddF, ReadVMask]>; +} + +multiclass VSQR_FV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFSqrtV, ReadVFSqrtV, ReadVMask]>; +} + +multiclass VRCP_FV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFRecpV, ReadVFRecpV, ReadVMask]>; +} + +multiclass VCMP_FV_V_F funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVFCmpV, ReadVFCmpV, ReadVFCmpV, ReadVMask]>; + def F : VALUVF, + Sched<[WriteVFCmpF, ReadVFCmpV, ReadVFCmpF, ReadVMask]>; +} + +multiclass VCMP_FV_F funct6, string vw = "v"> { + def F : VALUVF, + Sched<[WriteVFCmpF, ReadVFCmpV, ReadVFCmpF, ReadVMask]>; +} + +multiclass VSGNJ_FV_V_F funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVFSgnjV, ReadVFSgnjV, ReadVFSgnjV, ReadVMask]>; + def F : VALUVF, + Sched<[WriteVFSgnjF, ReadVFSgnjV, ReadVFSgnjF, ReadVMask]>; +} + +multiclass VCLS_FV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFClassV, ReadVFClassV, ReadVMask]>; +} + +multiclass VCVTF_IV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFCvtIToFV, ReadVFCvtIToFV, ReadVMask]>; +} + +multiclass VCVTI_FV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFCvtFToIV, ReadVFCvtFToIV, ReadVMask]>; +} + +multiclass VWCVTF_IV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFWCvtIToFV, ReadVFWCvtIToFV, ReadVMask]>; +} + +multiclass VWCVTI_FV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFWCvtFToIV, ReadVFWCvtFToIV, ReadVMask]>; +} + +multiclass VWCVTF_FV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFWCvtFToFV, ReadVFWCvtFToFV, ReadVMask]>; +} + +multiclass VNCVTF_IV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFNCvtIToFV, ReadVFNCvtIToFV, ReadVMask]>; +} + +multiclass VNCVTI_FV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFNCvtFToIV, ReadVFNCvtFToIV, ReadVMask]>; +} + +multiclass VNCVTF_FV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVFNCvtFToFV, ReadVFNCvtFToFV, ReadVMask]>; +} + +multiclass VRED_MV_V funct6> { + def _VS : VALUVV, + Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV0, ReadVMask]>; +} + +multiclass VWRED_IV_V funct6> { + def _VS : VALUVV, + Sched<[WriteVIWRedV, ReadVIWRedV, ReadVIWRedV0, ReadVMask]>; +} + +multiclass VRED_FV_V funct6> { + def _VS : VALUVV, + Sched<[WriteVFRedV, ReadVFRedV, ReadVFRedV0, ReadVMask]>; +} + +multiclass VREDO_FV_V funct6> { + def _VS : VALUVV, + Sched<[WriteVFRedOV, ReadVFRedOV, ReadVFRedOV0, ReadVMask]>; +} + +multiclass VWRED_FV_V funct6> { + def _VS : VALUVV, + Sched<[WriteVFWRedV, ReadVFWRedV, ReadVFWRedV0, ReadVMask]>; +} + +multiclass VWREDO_FV_V funct6> { + def _VS : VALUVV, + Sched<[WriteVFWRedOV, ReadVFWRedOV, ReadVFWRedOV0, ReadVMask]>; } -multiclass VALUr_FV_V_F funct6, string vw = "v"> { - def V : VALUrVV; - def F : VALUrVF; +multiclass VMALU_MV_Mask funct6, string vm = "v"> { + def M : VALUVVNoVm, + Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>; } -multiclass VALU_FV_V funct6> { - def _VS : VALUVV; +multiclass VMSFS_MV_V funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>; } -multiclass VALU_FV_VS2 funct6, bits<5> vs1> { - def "" : VALUVs2; +multiclass VMIOT_MV_V funct6, bits<5> vs1> { + def "" : VALUVs2, + Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>; +} + +multiclass VSHT_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVShiftV, ReadVShiftV, ReadVShiftV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVShiftX, ReadVShiftV, ReadVShiftX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVShiftI, ReadVShiftV, ReadVMask]>; +} + +multiclass VNSHT_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVNShiftV, ReadVNShiftV, ReadVNShiftV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVNShiftX, ReadVNShiftV, ReadVNShiftX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVNShiftI, ReadVNShiftV, ReadVMask]>; +} + +multiclass VCMP_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>; +} + +multiclass VCMP_IV_X_I funct6, Operand optype = simm5, string vw = "v"> { + def X : VALUVX, + Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>; +} + +multiclass VCMP_IV_V_X funct6, Operand optype = simm5, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>; +} + +multiclass VMUL_MV_V_X funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVIMulV, ReadVIMulV, ReadVIMulV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVIMulX, ReadVIMulV, ReadVIMulX, ReadVMask]>; +} + +multiclass VWMUL_MV_V_X funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVIWMulV, ReadVIWMulV, ReadVIWMulV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVIWMulX, ReadVIWMulV, ReadVIWMulX, ReadVMask]>; +} + +multiclass VDIV_MV_V_X funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVIDivV, ReadVIDivV, ReadVIDivV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVIDivX, ReadVIDivV, ReadVIDivX, ReadVMask]>; +} + +multiclass VSALU_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVSALUI, ReadVSALUV, ReadVMask]>; +} + +multiclass VSALU_IV_V_X funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>; +} + +multiclass VAALU_MV_V_X funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVAALUV, ReadVAALUV, ReadVAALUV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVAALUX, ReadVAALUV, ReadVAALUX, ReadVMask]>; +} + +multiclass VSMUL_IV_V_X funct6, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVSMulV, ReadVSMulV, ReadVSMulV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVSMulX, ReadVSMulV, ReadVSMulX, ReadVMask]>; +} + +multiclass VSSHF_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVSShiftV, ReadVSShiftV, ReadVSShiftV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVSShiftX, ReadVSShiftV, ReadVSShiftX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVSShiftI, ReadVSShiftV, ReadVMask]>; +} + +multiclass VNCLP_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVNClipV, ReadVNClipV, ReadVNClipV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVNClipX, ReadVNClipV, ReadVNClipX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVNClipI, ReadVNClipV, ReadVMask]>; +} + +multiclass VSLD_IV_X_I funct6, Operand optype = simm5, string vw = "v"> { + def X : VALUVX, + Sched<[WriteVISlideX, ReadVISlideV, ReadVISlideX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVISlideI, ReadVISlideV, ReadVMask]>; +} + +multiclass VSLD1_MV_X funct6, string vw = "v"> { + def X : VALUVX, + Sched<[WriteVISlide1X, ReadVISlideV, ReadVISlideX, ReadVMask]>; +} + +multiclass VSLD1_FV_F funct6, string vw = "v"> { + def F : VALUVF, + Sched<[WriteVFSlide1F, ReadVFSlideV, ReadVFSlideF, ReadVMask]>; +} + +multiclass VGTR_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { + def V : VALUVV, + Sched<[WriteVGatherV, ReadVGatherV, ReadVGatherV, ReadVMask]>; + def X : VALUVX, + Sched<[WriteVGatherX, ReadVGatherV, ReadVGatherX, ReadVMask]>; + def I : VALUVI, + Sched<[WriteVGatherI, ReadVGatherV, ReadVMask]>; +} + +multiclass VCPR_MV_Mask funct6, string vm = "v"> { + def M : VALUVVNoVm, + Sched<[WriteVCompressV, ReadVCompressV, ReadVCompressV]>; } multiclass VAMO { @@ -435,11 +779,48 @@ def _UNWD : VAMONoWd; } -multiclass VWholeLoad nf, string opcodestr, RegisterClass VRC> { - def E8_V : VWholeLoad; - def E16_V : VWholeLoad; - def E32_V : VWholeLoad; - def E64_V : VWholeLoad; +multiclass VWholeLoad1 { + def E8_V : VWholeLoad<0, LSWidth8, opcodestr # "e8.v", VRC>, + Sched<[WriteVLD1R8, ReadVLDX]>; + def E16_V : VWholeLoad<0, LSWidth16, opcodestr # "e16.v", VRC>, + Sched<[WriteVLD1R16, ReadVLDX]>; + def E32_V : VWholeLoad<0, LSWidth32, opcodestr # "e32.v", VRC>, + Sched<[WriteVLD1R32, ReadVLDX]>; + def E64_V : VWholeLoad<0, LSWidth64, opcodestr # "e64.v", VRC>, + Sched<[WriteVLD1R64, ReadVLDX]>; +} + +multiclass VWholeLoad2 { + def E8_V : VWholeLoad<1, LSWidth8, opcodestr # "e8.v", VRC>, + Sched<[WriteVLD2R8, ReadVLDX]>; + def E16_V : VWholeLoad<1, LSWidth16, opcodestr # "e16.v", VRC>, + Sched<[WriteVLD2R16, ReadVLDX]>; + def E32_V : VWholeLoad<1, LSWidth32, opcodestr # "e32.v", VRC>, + Sched<[WriteVLD2R32, ReadVLDX]>; + def E64_V : VWholeLoad<1, LSWidth64, opcodestr # "e64.v", VRC>, + Sched<[WriteVLD2R64, ReadVLDX]>; +} + +multiclass VWholeLoad4 { + def E8_V : VWholeLoad<3, LSWidth8, opcodestr # "e8.v", VRC>, + Sched<[WriteVLD4R8, ReadVLDX]>; + def E16_V : VWholeLoad<3, LSWidth16, opcodestr # "e16.v", VRC>, + Sched<[WriteVLD4R16, ReadVLDX]>; + def E32_V : VWholeLoad<3, LSWidth32, opcodestr # "e32.v", VRC>, + Sched<[WriteVLD4R32, ReadVLDX]>; + def E64_V : VWholeLoad<3, LSWidth64, opcodestr # "e64.v", VRC>, + Sched<[WriteVLD1R64, ReadVLDX]>; +} + +multiclass VWholeLoad8 { + def E8_V : VWholeLoad<7, LSWidth8, opcodestr # "e8.v", VRC>, + Sched<[WriteVLD8R8, ReadVLDX]>; + def E16_V : VWholeLoad<7, LSWidth16, opcodestr # "e16.v", VRC>, + Sched<[WriteVLD8R16, ReadVLDX]>; + def E32_V : VWholeLoad<7, LSWidth32, opcodestr # "e32.v", VRC>, + Sched<[WriteVLD8R32, ReadVLDX]>; + def E64_V : VWholeLoad<7, LSWidth64, opcodestr # "e64.v", VRC>, + Sched<[WriteVLD8R64, ReadVLDX]>; } //===----------------------------------------------------------------------===// @@ -459,69 +840,94 @@ } // hasSideEffects = 1, mayLoad = 0, mayStore = 0 // Vector Unit-Stride Instructions -def VLE8_V : VUnitStrideLoad; -def VLE16_V : VUnitStrideLoad; -def VLE32_V : VUnitStrideLoad; -def VLE64_V : VUnitStrideLoad; - -def VLE8FF_V : VUnitStrideLoad; -def VLE16FF_V : VUnitStrideLoad; -def VLE32FF_V : VUnitStrideLoad; -def VLE64FF_V : VUnitStrideLoad; - -def VLE1_V : VUnitStrideLoadMask<"vle1.v">; -def VSE1_V : VUnitStrideStoreMask<"vse1.v">; - -def VSE8_V : VUnitStrideStore; -def VSE16_V : VUnitStrideStore; -def VSE32_V : VUnitStrideStore; -def VSE64_V : VUnitStrideStore; +def VLE8_V : VUnitStrideLoad, + VLESched<8>; +def VLE16_V : VUnitStrideLoad, + VLESched<16>; +def VLE32_V : VUnitStrideLoad, + VLESched<32>; +def VLE64_V : VUnitStrideLoad, + VLESched<64>; + +def VLE8FF_V : VUnitStrideLoad, + VLFSched<8>; +def VLE16FF_V : VUnitStrideLoad, + VLFSched<16>; +def VLE32FF_V : VUnitStrideLoad, + VLFSched<32>; +def VLE64FF_V : VUnitStrideLoad, + VLFSched<64>; + +def VLE1_V : VUnitStrideLoadMask<"vle1.v">, + Sched<[WriteVLDM, ReadVLDX]>; +def VSE1_V : VUnitStrideStoreMask<"vse1.v">, + Sched<[WriteVSTM, ReadVSTM, ReadVSTX]>; + +def VSE8_V : VUnitStrideStore, + VSESched<8>; +def VSE16_V : VUnitStrideStore, + VSESched<16>; +def VSE32_V : VUnitStrideStore, + VSESched<32>; +def VSE64_V : VUnitStrideStore, + VSESched<64>; // Vector Strided Instructions -def VLSE8_V : VStridedLoad; -def VLSE16_V : VStridedLoad; -def VLSE32_V : VStridedLoad; -def VLSE64_V : VStridedLoad; - -def VSSE8_V : VStridedStore; -def VSSE16_V : VStridedStore; -def VSSE32_V : VStridedStore; -def VSSE64_V : VStridedStore; +def VLSE8_V : VStridedLoad, + VLSSched<8>; +def VLSE16_V : VStridedLoad, + VLSSched<16>; +def VLSE32_V : VStridedLoad, + VLSSched<32>; +def VLSE64_V : VStridedLoad, + VLSSched<32>; + +def VSSE8_V : VStridedStore, + VSSSched<8>; +def VSSE16_V : VStridedStore, + VSSSched<16>; +def VSSE32_V : VStridedStore, + VSSSched<32>; +def VSSE64_V : VStridedStore, + VSSSched<64>; // Vector Indexed Instructions -def VLUXEI8_V : VIndexedLoad; -def VLUXEI16_V : VIndexedLoad; -def VLUXEI32_V : VIndexedLoad; -def VLUXEI64_V : VIndexedLoad; - -def VLOXEI8_V : VIndexedLoad; -def VLOXEI16_V : VIndexedLoad; -def VLOXEI32_V : VIndexedLoad; -def VLOXEI64_V : VIndexedLoad; - -def VSUXEI8_V : VIndexedStore; -def VSUXEI16_V : VIndexedStore; -def VSUXEI32_V : VIndexedStore; -def VSUXEI64_V : VIndexedStore; - -def VSOXEI8_V : VIndexedStore; -def VSOXEI16_V : VIndexedStore; -def VSOXEI32_V : VIndexedStore; -def VSOXEI64_V : VIndexedStore; - -defm VL1R : VWholeLoad<0, "vl1r", VR>; -defm VL2R : VWholeLoad<1, "vl2r", VRM2>; -defm VL4R : VWholeLoad<3, "vl4r", VRM4>; -defm VL8R : VWholeLoad<7, "vl8r", VRM8>; +foreach n = [8, 16, 32, 64] in { +defvar w = !cast("LSWidth" # n); + +def VLUXEI # n # _V : + VIndexedLoad, + VLXSched; +def VLOXEI # n # _V : + VIndexedLoad, + VLXSched; + +def VSUXEI # n # _V : + VIndexedStore, + VSXSched; +def VSOXEI # n # _V : + VIndexedStore, + VSXSched; +} + +defm VL1R : VWholeLoad1<"vl1r", VR>; +defm VL2R : VWholeLoad2<"vl2r", VRM2>; +defm VL4R : VWholeLoad4<"vl4r", VRM4>; +defm VL8R : VWholeLoad8<"vl8r", VRM8>; + def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>; def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>; def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>; -def VS1R_V : VWholeStore<0, "vs1r.v", VR>; -def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>; -def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>; -def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>; +def VS1R_V : VWholeStore<0, "vs1r.v", VR>, + Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>; +def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>, + Sched<[WriteVST2R, ReadVST2R, ReadVSTX]>; +def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>, + Sched<[WriteVST4R, ReadVST4R, ReadVSTX]>; +def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>, + Sched<[WriteVST8R, ReadVST8R, ReadVSTX]>; // Vector Single-Width Integer Add and Subtract defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; @@ -588,9 +994,9 @@ (VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>; // Vector Single-Width Bit Shift Instructions -defm VSLL_V : VALU_IV_V_X_I<"vsll", 0b100101, uimm5>; -defm VSRL_V : VALU_IV_V_X_I<"vsrl", 0b101000, uimm5>; -defm VSRA_V : VALU_IV_V_X_I<"vsra", 0b101001, uimm5>; +defm VSLL_V : VSHT_IV_V_X_I<"vsll", 0b100101, uimm5>; +defm VSRL_V : VSHT_IV_V_X_I<"vsrl", 0b101000, uimm5>; +defm VSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001, uimm5>; // Vector Narrowing Integer Right Shift Instructions // Refer to 11.3. Narrowing Vector Arithmetic Instructions @@ -598,8 +1004,8 @@ // vector register group (specified by vs2). The destination vector register // group cannot overlap the mask register if used, unless LMUL=1. let Constraints = "@earlyclobber $vd" in { -defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">; -defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">; +defm VNSRL_W : VNSHT_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">; +defm VNSRA_W : VNSHT_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">; } // Constraints = "@earlyclobber $vd" def : InstAlias<"vncvt.x.x.w $vd, $vs$vm", @@ -607,14 +1013,14 @@ // Vector Integer Comparison Instructions let RVVConstraint = NoConstraint in { -defm VMSEQ_V : VALU_IV_V_X_I<"vmseq", 0b011000>; -defm VMSNE_V : VALU_IV_V_X_I<"vmsne", 0b011001>; -defm VMSLTU_V : VALU_IV_V_X<"vmsltu", 0b011010>; -defm VMSLT_V : VALU_IV_V_X<"vmslt", 0b011011>; -defm VMSLEU_V : VALU_IV_V_X_I<"vmsleu", 0b011100>; -defm VMSLE_V : VALU_IV_V_X_I<"vmsle", 0b011101>; -defm VMSGTU_V : VALU_IV_X_I<"vmsgtu", 0b011110>; -defm VMSGT_V : VALU_IV_X_I<"vmsgt", 0b011111>; +defm VMSEQ_V : VCMP_IV_V_X_I<"vmseq", 0b011000>; +defm VMSNE_V : VCMP_IV_V_X_I<"vmsne", 0b011001>; +defm VMSLTU_V : VCMP_IV_V_X<"vmsltu", 0b011010>; +defm VMSLT_V : VCMP_IV_V_X<"vmslt", 0b011011>; +defm VMSLEU_V : VCMP_IV_V_X_I<"vmsleu", 0b011100>; +defm VMSLE_V : VCMP_IV_V_X_I<"vmsle", 0b011101>; +defm VMSGTU_V : VCMP_IV_X_I<"vmsgtu", 0b011110>; +defm VMSGT_V : VCMP_IV_X_I<"vmsgt", 0b011111>; } // RVVConstraint = NoConstraint def : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm", @@ -672,84 +1078,87 @@ } // Vector Integer Min/Max Instructions -defm VMINU_V : VALU_IV_V_X<"vminu", 0b000100>; -defm VMIN_V : VALU_IV_V_X<"vmin", 0b000101>; -defm VMAXU_V : VALU_IV_V_X<"vmaxu", 0b000110>; -defm VMAX_V : VALU_IV_V_X<"vmax", 0b000111>; +defm VMINU_V : VCMP_IV_V_X<"vminu", 0b000100>; +defm VMIN_V : VCMP_IV_V_X<"vmin", 0b000101>; +defm VMAXU_V : VCMP_IV_V_X<"vmaxu", 0b000110>; +defm VMAX_V : VCMP_IV_V_X<"vmax", 0b000111>; // Vector Single-Width Integer Multiply Instructions -defm VMUL_V : VALU_MV_V_X<"vmul", 0b100101>; -defm VMULH_V : VALU_MV_V_X<"vmulh", 0b100111>; -defm VMULHU_V : VALU_MV_V_X<"vmulhu", 0b100100>; -defm VMULHSU_V : VALU_MV_V_X<"vmulhsu", 0b100110>; +defm VMUL_V : VMUL_MV_V_X<"vmul", 0b100101>; +defm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>; +defm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>; +defm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>; // Vector Integer Divide Instructions -defm VDIVU_V : VALU_MV_V_X<"vdivu", 0b100000>; -defm VDIV_V : VALU_MV_V_X<"vdiv", 0b100001>; -defm VREMU_V : VALU_MV_V_X<"vremu", 0b100010>; -defm VREM_V : VALU_MV_V_X<"vrem", 0b100011>; +defm VDIVU_V : VDIV_MV_V_X<"vdivu", 0b100000>; +defm VDIV_V : VDIV_MV_V_X<"vdiv", 0b100001>; +defm VREMU_V : VDIV_MV_V_X<"vremu", 0b100010>; +defm VREM_V : VDIV_MV_V_X<"vrem", 0b100011>; // Vector Widening Integer Multiply Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { -defm VWMUL_V : VALU_MV_V_X<"vwmul", 0b111011>; -defm VWMULU_V : VALU_MV_V_X<"vwmulu", 0b111000>; -defm VWMULSU_V : VALU_MV_V_X<"vwmulsu", 0b111010>; +defm VWMUL_V : VWMUL_MV_V_X<"vwmul", 0b111011>; +defm VWMULU_V : VWMUL_MV_V_X<"vwmulu", 0b111000>; +defm VWMULSU_V : VWMUL_MV_V_X<"vwmulsu", 0b111010>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV // Vector Single-Width Integer Multiply-Add Instructions -defm VMACC_V : VALUr_MV_V_X<"vmacc", 0b101101>; -defm VNMSAC_V : VALUr_MV_V_X<"vnmsac", 0b101111>; -defm VMADD_V : VALUr_MV_V_X<"vmadd", 0b101001>; -defm VNMSUB_V : VALUr_MV_V_X<"vnmsub", 0b101011>; +defm VMACC_V : VMAC_MV_V_X<"vmacc", 0b101101>; +defm VNMSAC_V : VMAC_MV_V_X<"vnmsac", 0b101111>; +defm VMADD_V : VMAC_MV_V_X<"vmadd", 0b101001>; +defm VNMSUB_V : VMAC_MV_V_X<"vnmsub", 0b101011>; // Vector Widening Integer Multiply-Add Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { -defm VWMACCU_V : VALUr_MV_V_X<"vwmaccu", 0b111100>; -defm VWMACC_V : VALUr_MV_V_X<"vwmacc", 0b111101>; -defm VWMACCSU_V : VALUr_MV_V_X<"vwmaccsu", 0b111111>; -defm VWMACCUS_V : VALUr_MV_X<"vwmaccus", 0b111110>; +defm VWMACCU_V : VWMAC_MV_V_X<"vwmaccu", 0b111100>; +defm VWMACC_V : VWMAC_MV_V_X<"vwmacc", 0b111101>; +defm VWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111111>; +defm VWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111110>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV // Vector Integer Merge Instructions -defm VMERGE_V : VALUm_IV_V_X_I<"vmerge", 0b010111>; +defm VMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>; // Vector Integer Move Instructions let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1, RVVConstraint = NoConstraint in { // op vd, vs1 def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd), - (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">; + (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">, + Sched<[WriteVIMovV, ReadVIMovV]>; // op vd, rs1 def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd), - (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">; + (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">, + Sched<[WriteVIMovX, ReadVIMovX]>; // op vd, imm def VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd), - (ins simm5:$imm), "vmv.v.i", "$vd, $imm">; + (ins simm5:$imm), "vmv.v.i", "$vd, $imm">, + Sched<[WriteVIMovI]>; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 // Vector Fixed-Point Arithmetic Instructions -defm VSADDU_V : VALU_IV_V_X_I<"vsaddu", 0b100000>; -defm VSADD_V : VALU_IV_V_X_I<"vsadd", 0b100001>; -defm VSSUBU_V : VALU_IV_V_X<"vssubu", 0b100010>; -defm VSSUB_V : VALU_IV_V_X<"vssub", 0b100011>; +defm VSADDU_V : VSALU_IV_V_X_I<"vsaddu", 0b100000>; +defm VSADD_V : VSALU_IV_V_X_I<"vsadd", 0b100001>; +defm VSSUBU_V : VSALU_IV_V_X<"vssubu", 0b100010>; +defm VSSUB_V : VSALU_IV_V_X<"vssub", 0b100011>; // Vector Single-Width Averaging Add and Subtract -defm VAADDU_V : VALU_MV_V_X<"vaaddu", 0b001000>; -defm VAADD_V : VALU_MV_V_X<"vaadd", 0b001001>; -defm VASUBU_V : VALU_MV_V_X<"vasubu", 0b001010>; -defm VASUB_V : VALU_MV_V_X<"vasub", 0b001011>; +defm VAADDU_V : VAALU_MV_V_X<"vaaddu", 0b001000>; +defm VAADD_V : VAALU_MV_V_X<"vaadd", 0b001001>; +defm VASUBU_V : VAALU_MV_V_X<"vasubu", 0b001010>; +defm VASUB_V : VAALU_MV_V_X<"vasub", 0b001011>; // Vector Single-Width Fractional Multiply with Rounding and Saturation -defm VSMUL_V : VALU_IV_V_X<"vsmul", 0b100111>; +defm VSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>; // Vector Single-Width Scaling Shift Instructions -defm VSSRL_V : VALU_IV_V_X_I<"vssrl", 0b101010, uimm5>; -defm VSSRA_V : VALU_IV_V_X_I<"vssra", 0b101011, uimm5>; +defm VSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010, uimm5>; +defm VSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011, uimm5>; // Vector Narrowing Fixed-Point Clip Instructions let Constraints = "@earlyclobber $vd" in { -defm VNCLIPU_W : VALU_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">; -defm VNCLIP_W : VALU_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">; +defm VNCLIPU_W : VNCLP_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">; +defm VNCLIP_W : VNCLP_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">; } // Constraints = "@earlyclobber $vd" } // Predicates = [HasStdExtV] @@ -762,60 +1171,60 @@ // Vector Widening Floating-Point Add/Subtract Instructions let Constraints = "@earlyclobber $vd" in { let RVVConstraint = WidenV in { -defm VFWADD_V : VALU_FV_V_F<"vfwadd", 0b110000>; -defm VFWSUB_V : VALU_FV_V_F<"vfwsub", 0b110010>; +defm VFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000>; +defm VFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010>; } // RVVConstraint = WidenV // Set earlyclobber for following instructions for second and mask operands. // This has the downside that the earlyclobber constraint is too coarse and // will impose unnecessary restrictions by not allowing the destination to // overlap with the first (wide) operand. let RVVConstraint = WidenW in { -defm VFWADD_W : VALU_FV_V_F<"vfwadd", 0b110100, "w">; -defm VFWSUB_W : VALU_FV_V_F<"vfwsub", 0b110110, "w">; +defm VFWADD_W : VWALU_FV_V_F<"vfwadd", 0b110100, "w">; +defm VFWSUB_W : VWALU_FV_V_F<"vfwsub", 0b110110, "w">; } // RVVConstraint = WidenW } // Constraints = "@earlyclobber $vd" // Vector Single-Width Floating-Point Multiply/Divide Instructions -defm VFMUL_V : VALU_FV_V_F<"vfmul", 0b100100>; -defm VFDIV_V : VALU_FV_V_F<"vfdiv", 0b100000>; -defm VFRDIV_V : VALU_FV_F<"vfrdiv", 0b100001>; +defm VFMUL_V : VMUL_FV_V_F<"vfmul", 0b100100>; +defm VFDIV_V : VDIV_FV_V_F<"vfdiv", 0b100000>; +defm VFRDIV_V : VRDIV_FV_F<"vfrdiv", 0b100001>; // Vector Widening Floating-Point Multiply let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { -defm VFWMUL_V : VALU_FV_V_F<"vfwmul", 0b111000>; +defm VFWMUL_V : VWMUL_FV_V_F<"vfwmul", 0b111000>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV // Vector Single-Width Floating-Point Fused Multiply-Add Instructions -defm VFMACC_V : VALUr_FV_V_F<"vfmacc", 0b101100>; -defm VFNMACC_V : VALUr_FV_V_F<"vfnmacc", 0b101101>; -defm VFMSAC_V : VALUr_FV_V_F<"vfmsac", 0b101110>; -defm VFNMSAC_V : VALUr_FV_V_F<"vfnmsac", 0b101111>; -defm VFMADD_V : VALUr_FV_V_F<"vfmadd", 0b101000>; -defm VFNMADD_V : VALUr_FV_V_F<"vfnmadd", 0b101001>; -defm VFMSUB_V : VALUr_FV_V_F<"vfmsub", 0b101010>; -defm VFNMSUB_V : VALUr_FV_V_F<"vfnmsub", 0b101011>; +defm VFMACC_V : VMAC_FV_V_F<"vfmacc", 0b101100>; +defm VFNMACC_V : VMAC_FV_V_F<"vfnmacc", 0b101101>; +defm VFMSAC_V : VMAC_FV_V_F<"vfmsac", 0b101110>; +defm VFNMSAC_V : VMAC_FV_V_F<"vfnmsac", 0b101111>; +defm VFMADD_V : VMAC_FV_V_F<"vfmadd", 0b101000>; +defm VFNMADD_V : VMAC_FV_V_F<"vfnmadd", 0b101001>; +defm VFMSUB_V : VMAC_FV_V_F<"vfmsub", 0b101010>; +defm VFNMSUB_V : VMAC_FV_V_F<"vfnmsub", 0b101011>; // Vector Widening Floating-Point Fused Multiply-Add Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { -defm VFWMACC_V : VALUr_FV_V_F<"vfwmacc", 0b111100>; -defm VFWNMACC_V : VALUr_FV_V_F<"vfwnmacc", 0b111101>; -defm VFWMSAC_V : VALUr_FV_V_F<"vfwmsac", 0b111110>; -defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>; +defm VFWMACC_V : VWMAC_FV_V_F<"vfwmacc", 0b111100>; +defm VFWNMACC_V : VWMAC_FV_V_F<"vfwnmacc", 0b111101>; +defm VFWMSAC_V : VWMAC_FV_V_F<"vfwmsac", 0b111110>; +defm VFWNMSAC_V : VWMAC_FV_V_F<"vfwnmsac", 0b111111>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV // Vector Floating-Point Square-Root Instruction -defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>; -defm VFRSQRT7_V : VALU_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>; -defm VFREC7_V : VALU_FV_VS2<"vfrec7.v", 0b010011, 0b00101>; +defm VFSQRT_V : VSQR_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>; +defm VFRSQRT7_V : VRCP_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>; +defm VFREC7_V : VRCP_FV_VS2<"vfrec7.v", 0b010011, 0b00101>; // Vector Floating-Point MIN/MAX Instructions -defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>; -defm VFMAX_V : VALU_FV_V_F<"vfmax", 0b000110>; +defm VFMIN_V : VCMP_FV_V_F<"vfmin", 0b000100>; +defm VFMAX_V : VCMP_FV_V_F<"vfmax", 0b000110>; // Vector Floating-Point Sign-Injection Instructions -defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>; -defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>; -defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>; +defm VFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>; +defm VFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>; +defm VFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>; def : InstAlias<"vfneg.v $vd, $vs$vm", (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>; @@ -824,12 +1233,12 @@ // Vector Floating-Point Compare Instructions let RVVConstraint = NoConstraint in { -defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>; -defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>; -defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>; -defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>; -defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>; -defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>; +defm VMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>; +defm VMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>; +defm VMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>; +defm VMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>; +defm VMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>; +defm VMFGE_V : VCMP_FV_F<"vmfge", 0b011111>; } // RVVConstraint = NoConstraint def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm", @@ -838,68 +1247,70 @@ (VMFLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; // Vector Floating-Point Classify Instruction -defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b010011, 0b10000>; +defm VFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b010011, 0b10000>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { + // Vector Floating-Point Merge Instruction +let vm = 0 in def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd), (ins VR:$vs2, FPR32:$rs1, VMV0:$v0), - "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> { - let vm = 0; -} + "vfmerge.vfm", "$vd, $vs2, $rs1, v0">, + Sched<[WriteVFMergeV, ReadVFMergeV, ReadVFMergeF, ReadVMask]>; // Vector Floating-Point Move Instruction let RVVConstraint = NoConstraint in +let vm = 1, vs2 = 0 in def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd), - (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> { - let vs2 = 0; - let vm = 1; -} + (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">, + Sched<[WriteVFMovV, ReadVFMovF]>; + } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 // Single-Width Floating-Point/Integer Type-Convert Instructions -defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>; -defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>; -defm VFCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>; -defm VFCVT_RTZ_X_F_V : VALU_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>; -defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>; -defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>; +defm VFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>; +defm VFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>; +defm VFCVT_RTZ_XU_F_V : VCVTI_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>; +defm VFCVT_RTZ_X_F_V : VCVTI_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>; +defm VFCVT_F_XU_V : VCVTF_IV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>; +defm VFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>; // Widening Floating-Point/Integer Type-Convert Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in { -defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>; -defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>; -defm VFWCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>; -defm VFWCVT_RTZ_X_F_V : VALU_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>; -defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>; -defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>; -defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>; +defm VFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>; +defm VFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>; +defm VFWCVT_RTZ_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>; +defm VFWCVT_RTZ_X_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>; +defm VFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>; +defm VFWCVT_F_X_V : VWCVTF_IV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>; +defm VFWCVT_F_F_V : VWCVTF_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt // Narrowing Floating-Point/Integer Type-Convert Instructions let Constraints = "@earlyclobber $vd" in { -defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>; -defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>; -defm VFNCVT_RTZ_XU_F_W : VALU_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>; -defm VFNCVT_RTZ_X_F_W : VALU_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>; -defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>; -defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>; -defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>; -defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>; +defm VFNCVT_XU_F_W : VNCVTI_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>; +defm VFNCVT_X_F_W : VNCVTI_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>; +defm VFNCVT_RTZ_XU_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>; +defm VFNCVT_RTZ_X_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>; +defm VFNCVT_F_XU_W : VNCVTF_IV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>; +defm VFNCVT_F_X_W : VNCVTF_IV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>; +defm VFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>; +defm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>; } // Constraints = "@earlyclobber $vd" } // Predicates = [HasStdExtV, HasStdExtF] let Predicates = [HasStdExtV] in { + // Vector Single-Width Integer Reduction Instructions let RVVConstraint = NoConstraint in { -defm VREDSUM : VALU_MV_V<"vredsum", 0b000000>; -defm VREDMAXU : VALU_MV_V<"vredmaxu", 0b000110>; -defm VREDMAX : VALU_MV_V<"vredmax", 0b000111>; -defm VREDMINU : VALU_MV_V<"vredminu", 0b000100>; -defm VREDMIN : VALU_MV_V<"vredmin", 0b000101>; -defm VREDAND : VALU_MV_V<"vredand", 0b000001>; -defm VREDOR : VALU_MV_V<"vredor", 0b000010>; -defm VREDXOR : VALU_MV_V<"vredxor", 0b000011>; +defm VREDSUM : VRED_MV_V<"vredsum", 0b000000>; +defm VREDMAXU : VRED_MV_V<"vredmaxu", 0b000110>; +defm VREDMAX : VRED_MV_V<"vredmax", 0b000111>; +defm VREDMINU : VRED_MV_V<"vredminu", 0b000100>; +defm VREDMIN : VRED_MV_V<"vredmin", 0b000101>; +defm VREDAND : VRED_MV_V<"vredand", 0b000001>; +defm VREDOR : VRED_MV_V<"vredor", 0b000010>; +defm VREDXOR : VRED_MV_V<"vredxor", 0b000011>; } // RVVConstraint = NoConstraint // Vector Widening Integer Reduction Instructions @@ -908,18 +1319,19 @@ // This has the downside that the earlyclobber constraint is too coarse and // will impose unnecessary restrictions by not allowing the destination to // overlap with the first (wide) operand. -defm VWREDSUMU : VALU_IV_V<"vwredsumu", 0b110000>; -defm VWREDSUM : VALU_IV_V<"vwredsum", 0b110001>; +defm VWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>; +defm VWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>; } // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint + } // Predicates = [HasStdExtV] let Predicates = [HasStdExtV, HasStdExtF] in { // Vector Single-Width Floating-Point Reduction Instructions let RVVConstraint = NoConstraint in { -defm VFREDOSUM : VALU_FV_V<"vfredosum", 0b000011>; -defm VFREDSUM : VALU_FV_V<"vfredsum", 0b000001>; -defm VFREDMAX : VALU_FV_V<"vfredmax", 0b000111>; -defm VFREDMIN : VALU_FV_V<"vfredmin", 0b000101>; +defm VFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>; +defm VFREDSUM : VRED_FV_V<"vfredsum", 0b000001>; +defm VFREDMAX : VRED_FV_V<"vfredmax", 0b000111>; +defm VFREDMIN : VRED_FV_V<"vfredmin", 0b000101>; } // RVVConstraint = NoConstraint // Vector Widening Floating-Point Reduction Instructions @@ -928,22 +1340,22 @@ // This has the downside that the earlyclobber constraint is too coarse and // will impose unnecessary restrictions by not allowing the destination to // overlap with the first (wide) operand. -defm VFWREDOSUM : VALU_FV_V<"vfwredosum", 0b110011>; -defm VFWREDSUM : VALU_FV_V<"vfwredsum", 0b110001>; +defm VFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>; +defm VFWREDSUM : VWRED_FV_V<"vfwredsum", 0b110001>; } // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint } // Predicates = [HasStdExtV, HasStdExtF] let Predicates = [HasStdExtV] in { // Vector Mask-Register Logical Instructions let RVVConstraint = NoConstraint in { -defm VMAND_M : VALU_MV_Mask<"vmand", 0b011001, "m">; -defm VMNAND_M : VALU_MV_Mask<"vmnand", 0b011101, "m">; -defm VMANDNOT_M : VALU_MV_Mask<"vmandnot", 0b011000, "m">; -defm VMXOR_M : VALU_MV_Mask<"vmxor", 0b011011, "m">; -defm VMOR_M : VALU_MV_Mask<"vmor", 0b011010, "m">; -defm VMNOR_M : VALU_MV_Mask<"vmnor", 0b011110, "m">; -defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">; -defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">; +defm VMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">; +defm VMNAND_M : VMALU_MV_Mask<"vmnand", 0b011101, "m">; +defm VMANDNOT_M : VMALU_MV_Mask<"vmandnot", 0b011000, "m">; +defm VMXOR_M : VMALU_MV_Mask<"vmxor", 0b011011, "m">; +defm VMOR_M : VMALU_MV_Mask<"vmor", 0b011010, "m">; +defm VMNOR_M : VMALU_MV_Mask<"vmnor", 0b011110, "m">; +defm VMORNOT_M : VMALU_MV_Mask<"vmornot", 0b011100, "m">; +defm VMXNOR_M : VMALU_MV_Mask<"vmxnor", 0b011111, "m">; } def : InstAlias<"vmmv.m $vd, $vs", @@ -957,98 +1369,113 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, RVVConstraint = NoConstraint in { + // Vector mask population count vpopc def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd), - (ins VR:$vs2, VMaskOp:$vm), - "vpopc.m", "$vd, $vs2$vm">; + (ins VR:$vs2, VMaskOp:$vm), + "vpopc.m", "$vd, $vs2$vm">, + Sched<[WriteVMPopV, ReadVMPopV, ReadVMask]>; // vfirst find-first-set mask bit def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd), - (ins VR:$vs2, VMaskOp:$vm), - "vfirst.m", "$vd, $vs2$vm">; + (ins VR:$vs2, VMaskOp:$vm), + "vfirst.m", "$vd, $vs2$vm">, + Sched<[WriteVMFFSV, ReadVMFFSV, ReadVMask]>; + } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { + // vmsbf.m set-before-first mask bit -defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>; +defm VMSBF_M : VMSFS_MV_V<"vmsbf.m", 0b010100, 0b00001>; // vmsif.m set-including-first mask bit -defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>; +defm VMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010100, 0b00011>; // vmsof.m set-only-first mask bit -defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>; +defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>; // Vector Iota Instruction -defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>; +defm VIOTA_M : VMIOT_MV_V<"viota.m", 0b010100, 0b10000>; + } // Constraints = "@earlyclobber $vd", RVVConstraint = Iota // Vector Element Index Instruction let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { + +let vs2 = 0 in def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd), - (ins VMaskOp:$vm), "vid.v", "$vd$vm"> { - let vs2 = 0; -} + (ins VMaskOp:$vm), "vid.v", "$vd$vm">, + Sched<[WriteVMIdxV, ReadVMask]>; // Integer Scalar Move Instructions let vm = 1, RVVConstraint = NoConstraint in { def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd), - (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">; + (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">, + Sched<[WriteVIMovVX, ReadVIMovVX]>; let Constraints = "$vd = $vd_wb" in def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb), - (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">; - + (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">, + Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>; } + } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + } // Predicates = [HasStdExtV] let Predicates = [HasStdExtV, HasStdExtF] in { + let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1, RVVConstraint = NoConstraint in { // Floating-Point Scalar Move Instructions def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd), - (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">; + (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">, + Sched<[WriteVFMovVF, ReadVFMovVF]>; let Constraints = "$vd = $vd_wb" in def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb), - (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">; + (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">, + Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 + } // Predicates = [HasStdExtV, HasStdExtF] let Predicates = [HasStdExtV] in { // Vector Slide Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { -defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>; -defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>; +defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, uimm5>; +defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>; } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp -defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>; -defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>; +defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, uimm5>; +defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>; } // Predicates = [HasStdExtV] let Predicates = [HasStdExtV, HasStdExtF] in { let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { -defm VFSLIDE1UP_V : VALU_FV_F<"vfslide1up", 0b001110>; +defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>; } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp -defm VFSLIDE1DOWN_V : VALU_FV_F<"vfslide1down", 0b001111>; +defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>; } // Predicates = [HasStdExtV, HasStdExtF] let Predicates = [HasStdExtV] in { // Vector Register Gather Instruction let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in { -defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5>; -def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">; +defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100, uimm5>; +def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">, + Sched<[WriteVGatherV, ReadVGatherV, ReadVGatherV]>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather // Vector Compress Instruction let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in { -defm VCOMPRESS_V : VALU_MV_Mask<"vcompress", 0b010111>; +defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress let hasSideEffects = 0, mayLoad = 0, mayStore = 0, RVVConstraint = NoConstraint in { -foreach nf = [1, 2, 4, 8] in { - def VMV#nf#R_V : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VR:$vd), - (ins VR:$vs2), "vmv" # nf # "r.v", - "$vd, $vs2"> { - let Uses = []; - let vm = 1; - } +foreach n = [1, 2, 4, 8] in { + def VMV#n#R_V : RVInstV<0b100111, !add(n, -1), OPIVI, (outs VR:$vd), + (ins VR:$vs2), "vmv" # n # "r.v", "$vd, $vs2">, + VMVRSched { + let Uses = []; + let vm = 1; +} } } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasStdExtV] diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -231,6 +231,9 @@ def : ReadAdvance; def : ReadAdvance; +//===----------------------------------------------------------------------===// +// Unsupported extensions +defm : UnsupportedSchedV; defm : UnsupportedSchedZba; defm : UnsupportedSchedZbb; defm : UnsupportedSchedZfh; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -219,6 +219,9 @@ def : ReadAdvance; def : ReadAdvance; +//===----------------------------------------------------------------------===// +// Unsupported extensions +defm : UnsupportedSchedV; defm : UnsupportedSchedZba; defm : UnsupportedSchedZbb; defm : UnsupportedSchedZfh; diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td --- a/llvm/lib/Target/RISCV/RISCVSchedule.td +++ b/llvm/lib/Target/RISCV/RISCVSchedule.td @@ -230,3 +230,4 @@ // Include the scheduler resources for other instruction extensions. include "RISCVScheduleB.td" +include "RISCVScheduleV.td" diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -0,0 +1,820 @@ +//===-- RISCVScheduleV.td - RISCV Scheduling Definitions V -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +/// Define scheduler resources associated with def operands. + +// 7. Vector Loads and Stores +// 7.4. Vector Unit-Stride Instructions +def WriteVLDE8 : SchedWrite; +def WriteVLDE16 : SchedWrite; +def WriteVLDE32 : SchedWrite; +def WriteVLDE64 : SchedWrite; +def WriteVSTE8 : SchedWrite; +def WriteVSTE16 : SchedWrite; +def WriteVSTE32 : SchedWrite; +def WriteVSTE64 : SchedWrite; +// 7.4.1. Vector Unit-Strided Mask +def WriteVLDM : SchedWrite; +def WriteVSTM : SchedWrite; +// 7.5. Vector Strided Instructions +def WriteVLDS8 : SchedWrite; +def WriteVLDS16 : SchedWrite; +def WriteVLDS32 : SchedWrite; +def WriteVLDS64 : SchedWrite; +def WriteVSTS8 : SchedWrite; +def WriteVSTS16 : SchedWrite; +def WriteVSTS32 : SchedWrite; +def WriteVSTS64 : SchedWrite; +// 7.6. Vector Indexed Instructions +def WriteVLDUX8 : SchedWrite; +def WriteVLDUX16 : SchedWrite; +def WriteVLDUX32 : SchedWrite; +def WriteVLDUX64 : SchedWrite; +def WriteVLDOX8 : SchedWrite; +def WriteVLDOX16 : SchedWrite; +def WriteVLDOX32 : SchedWrite; +def WriteVLDOX64 : SchedWrite; +def WriteVSTUX8 : SchedWrite; +def WriteVSTUX16 : SchedWrite; +def WriteVSTUX32 : SchedWrite; +def WriteVSTUX64 : SchedWrite; +def WriteVSTOX8 : SchedWrite; +def WriteVSTOX16 : SchedWrite; +def WriteVSTOX32 : SchedWrite; +def WriteVSTOX64 : SchedWrite; +// 7.7. Vector Unit-stride Fault-Only-First Loads +def WriteVLDFF8 : SchedWrite; +def WriteVLDFF16 : SchedWrite; +def WriteVLDFF32 : SchedWrite; +def WriteVLDFF64 : SchedWrite; +// 7.9. Vector Whole Register Instructions +def WriteVLD1R8 : SchedWrite; +def WriteVLD1R16 : SchedWrite; +def WriteVLD1R32 : SchedWrite; +def WriteVLD1R64 : SchedWrite; +def WriteVLD2R8 : SchedWrite; +def WriteVLD2R16 : SchedWrite; +def WriteVLD2R32 : SchedWrite; +def WriteVLD2R64 : SchedWrite; +def WriteVLD4R8 : SchedWrite; +def WriteVLD4R16 : SchedWrite; +def WriteVLD4R32 : SchedWrite; +def WriteVLD4R64 : SchedWrite; +def WriteVLD8R8 : SchedWrite; +def WriteVLD8R16 : SchedWrite; +def WriteVLD8R32 : SchedWrite; +def WriteVLD8R64 : SchedWrite; +def WriteVST1R : SchedWrite; +def WriteVST2R : SchedWrite; +def WriteVST4R : SchedWrite; +def WriteVST8R : SchedWrite; + +// 11. Vector Integer Arithmetic Instructions +// 11.1. Vector Single-Width Integer Add and Subtract +// 11.5. Vector Bitwise Logical Instructions +def WriteVIALUV : SchedWrite; +def WriteVIALUX : SchedWrite; +def WriteVIALUI : SchedWrite; +// 11.2. Vector Widening Integer Add/Subtract +def WriteVIWALUV : SchedWrite; +def WriteVIWALUX : SchedWrite; +def WriteVIWALUI : SchedWrite; +// 11.3. Vector Integer Extension +def WriteVExtV : SchedWrite; +// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions +def WriteVICALUV : SchedWrite; +def WriteVICALUX : SchedWrite; +def WriteVICALUI : SchedWrite; +// 11.6. Vector Single-Width Bit Shift Instructions +def WriteVShiftV : SchedWrite; +def WriteVShiftX : SchedWrite; +def WriteVShiftI : SchedWrite; +// 11.7. Vector Narrowing Integer Right Shift Instructions +def WriteVNShiftV : SchedWrite; +def WriteVNShiftX : SchedWrite; +def WriteVNShiftI : SchedWrite; +// 11.8. Vector Integer Comparison Instructions +// 11.9. Vector Integer Min/Max Instructions +def WriteVICmpV : SchedWrite; +def WriteVICmpX : SchedWrite; +def WriteVICmpI : SchedWrite; +// 11.10. Vector Single-Width Integer Multiply Instructions +def WriteVIMulV : SchedWrite; +def WriteVIMulX : SchedWrite; +// 11.11. Vector Integer Divide Instructions +def WriteVIDivV : SchedWrite; +def WriteVIDivX : SchedWrite; +// 11.12. Vector Widening Integer Multiply Instructions +def WriteVIWMulV : SchedWrite; +def WriteVIWMulX : SchedWrite; +// 11.13. Vector Single-Width Integer Multiply-Add Instructions +def WriteVIMulAddV : SchedWrite; +def WriteVIMulAddX : SchedWrite; +// 11.14. Vector Widening Integer Multiply-Add Instructions +def WriteVIWMulAddV : SchedWrite; +def WriteVIWMulAddX : SchedWrite; +// 11.15. Vector Integer Merge Instructions +def WriteVIMergeV : SchedWrite; +def WriteVIMergeX : SchedWrite; +def WriteVIMergeI : SchedWrite; +// 11.16. Vector Integer Move Instructions +def WriteVIMovV : SchedWrite; +def WriteVIMovX : SchedWrite; +def WriteVIMovI : SchedWrite; + +// 12. Vector Fixed-Point Arithmetic Instructions +// 12.1. Vector Single-Width Saturating Add and Subtract +def WriteVSALUV : SchedWrite; +def WriteVSALUX : SchedWrite; +def WriteVSALUI : SchedWrite; +// 12.2. Vector Single-Width Averaging Add and Subtract +def WriteVAALUV : SchedWrite; +def WriteVAALUX : SchedWrite; +// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation +def WriteVSMulV : SchedWrite; +def WriteVSMulX : SchedWrite; +// 12.4. Vector Single-Width Scaling Shift Instructions +def WriteVSShiftV : SchedWrite; +def WriteVSShiftX : SchedWrite; +def WriteVSShiftI : SchedWrite; +// 12.5. Vector Narrowing Fixed-Point Clip Instructions +def WriteVNClipV : SchedWrite; +def WriteVNClipX : SchedWrite; +def WriteVNClipI : SchedWrite; + +// 13. Vector Floating-Point Instructions +// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions +def WriteVFALUV : SchedWrite; +def WriteVFALUF : SchedWrite; +// 13.3. Vector Widening Floating-Point Add/Subtract Instructions +def WriteVFWALUV : SchedWrite; +def WriteVFWALUF : SchedWrite; +// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions +def WriteVFMulV : SchedWrite; +def WriteVFMulF : SchedWrite; +def WriteVFDivV : SchedWrite; +def WriteVFDivF : SchedWrite; +// 13.5. Vector Widening Floating-Point Multiply +def WriteVFWMulV : SchedWrite; +def WriteVFWMulF : SchedWrite; +// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions +def WriteVFMulAddV : SchedWrite; +def WriteVFMulAddF : SchedWrite; +// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions +def WriteVFWMulAddV : SchedWrite; +def WriteVFWMulAddF : SchedWrite; +// 13.8. Vector Floating-Point Square-Root Instruction +def WriteVFSqrtV : SchedWrite; +// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction +// 13.10. Vector Floating-Point Reciprocal Estimate Instruction +def WriteVFRecpV : SchedWrite; +// 13.11. Vector Floating-Point MIN/MAX Instructions +// 13.13. Vector Floating-Point Compare Instructions +def WriteVFCmpV : SchedWrite; +def WriteVFCmpF : SchedWrite; +// 13.12. Vector Floating-Point Sign-Injection Instructions +def WriteVFSgnjV : SchedWrite; +def WriteVFSgnjF : SchedWrite; +// 13.14. Vector Floating-Point Classify Instruction +def WriteVFClassV : SchedWrite; +// 13.15. Vector Floating-Point Merge Instruction +def WriteVFMergeV : SchedWrite; +// 13.16. Vector Floating-Point Move Instruction +def WriteVFMovV : SchedWrite; +// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions +def WriteVFCvtIToFV : SchedWrite; +def WriteVFCvtFToIV : SchedWrite; +def WriteVFCvtFToFV : SchedWrite; +// 13.18. Widening Floating-Point/Integer Type-Convert Instructions +def WriteVFWCvtIToFV : SchedWrite; +def WriteVFWCvtFToIV : SchedWrite; +def WriteVFWCvtFToFV : SchedWrite; +// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions +def WriteVFNCvtIToFV : SchedWrite; +def WriteVFNCvtFToIV : SchedWrite; +def WriteVFNCvtFToFV : SchedWrite; + +// 14. Vector Reduction Operations +// 14.1. Vector Single-Width Integer Reduction Instructions +def WriteVIRedV : SchedWrite; +// 14.2. Vector Widening Integer Reduction Instructions +def WriteVIWRedV : SchedWrite; +// 14.3. Vector Single-Width Floating-Point Reduction Instructions +def WriteVFRedV : SchedWrite; +def WriteVFRedOV : SchedWrite; +// 14.4. Vector Widening Floating-Point Reduction Instructions +def WriteVFWRedV : SchedWrite; +def WriteVFWRedOV : SchedWrite; + +// 15. Vector Mask Instructions +// 15.1. Vector Mask-Register Logical Instructions +def WriteVMALUV : SchedWrite; +// 15.2. Vector Mask Population Count +def WriteVMPopV : SchedWrite; +// 15.3. Vector Find-First-Set Mask Bit +def WriteVMFFSV : SchedWrite; +// 15.4. Vector Set-Before-First Mask Bit +// 15.5. Vector Set-Including-First Mask Bit +// 15.6. Vector Set-only-First Mask Bit +def WriteVMSFSV : SchedWrite; +// 15.8. Vector Iota Instruction +def WriteVMIotV : SchedWrite; +// 15.9. Vector Element Index Instruction +def WriteVMIdxV : SchedWrite; + +// 16. Vector Permutation Instructions +// 16.1. Integer Scalar Move Instructions +def WriteVIMovVX : SchedWrite; +def WriteVIMovXV : SchedWrite; +// 16.2. Floating-Point Scalar Move Instructions +def WriteVFMovVF : SchedWrite; +def WriteVFMovFV : SchedWrite; +// 16.3. Vector Slide Instructions +def WriteVISlideX : SchedWrite; +def WriteVISlideI : SchedWrite; +def WriteVISlide1X : SchedWrite; +def WriteVFSlide1F : SchedWrite; +// 16.4. Vector Register Gather Instructions +def WriteVGatherV : SchedWrite; +def WriteVGatherX : SchedWrite; +def WriteVGatherI : SchedWrite; +// 16.5. Vector Compress Instruction +def WriteVCompressV : SchedWrite; +// 16.6. Whole Vector Register Move +def WriteVMov1V : SchedWrite; +def WriteVMov2V : SchedWrite; +def WriteVMov4V : SchedWrite; +def WriteVMov8V : SchedWrite; + +//===----------------------------------------------------------------------===// +/// Define scheduler resources associated with use operands. + +// 7. Vector Loads and Stores +def ReadVLDX : SchedRead; +def ReadVSTX : SchedRead; +// 7.4. Vector Unit-Stride Instructions +def ReadVSTE8V : SchedRead; +def ReadVSTE16V : SchedRead; +def ReadVSTE32V : SchedRead; +def ReadVSTE64V : SchedRead; +// 7.4.1. Vector Unit-Strided Mask +def ReadVSTM : SchedRead; +// 7.5. Vector Strided Instructions +def ReadVLDSX : SchedRead; +def ReadVSTSX : SchedRead; +def ReadVSTS8V : SchedRead; +def ReadVSTS16V : SchedRead; +def ReadVSTS32V : SchedRead; +def ReadVSTS64V : SchedRead; +// 7.6. Vector Indexed Instructions +def ReadVLDUXV : SchedRead; +def ReadVLDOXV : SchedRead; +def ReadVSTUX8 : SchedRead; +def ReadVSTUX16 : SchedRead; +def ReadVSTUX32 : SchedRead; +def ReadVSTUX64 : SchedRead; +def ReadVSTUXV : SchedRead; +def ReadVSTUX8V : SchedRead; +def ReadVSTUX16V : SchedRead; +def ReadVSTUX32V : SchedRead; +def ReadVSTUX64V : SchedRead; +def ReadVSTOX8 : SchedRead; +def ReadVSTOX16 : SchedRead; +def ReadVSTOX32 : SchedRead; +def ReadVSTOX64 : SchedRead; +def ReadVSTOXV : SchedRead; +def ReadVSTOX8V : SchedRead; +def ReadVSTOX16V : SchedRead; +def ReadVSTOX32V : SchedRead; +def ReadVSTOX64V : SchedRead; +// 7.9. Vector Whole Register Instructions +def ReadVST1R : SchedRead; +def ReadVST2R : SchedRead; +def ReadVST4R : SchedRead; +def ReadVST8R : SchedRead; + +// 11. Vector Integer Arithmetic Instructions +// 11.1. Vector Single-Width Integer Add and Subtract +// 11.5. Vector Bitwise Logical Instructions +def ReadVIALUV : SchedRead; +def ReadVIALUX : SchedRead; +// 11.2. Vector Widening Integer Add/Subtract +def ReadVIWALUV : SchedRead; +def ReadVIWALUX : SchedRead; +// 11.3. Vector Integer Extension +def ReadVExtV : SchedRead; +// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions +def ReadVIALUCV : SchedRead; +def ReadVIALUCX : SchedRead; +// 11.6. Vector Single-Width Bit Shift Instructions +def ReadVShiftV : SchedRead; +def ReadVShiftX : SchedRead; +// 11.7. Vector Narrowing Integer Right Shift Instructions +def ReadVNShiftV : SchedRead; +def ReadVNShiftX : SchedRead; +// 11.8. Vector Integer Comparison Instructions +// 11.9. Vector Integer Min/Max Instructions +def ReadVICmpV : SchedRead; +def ReadVICmpX : SchedRead; +// 11.10. Vector Single-Width Integer Multiply Instructions +def ReadVIMulV : SchedRead; +def ReadVIMulX : SchedRead; +// 11.11. Vector Integer Divide Instructions +def ReadVIDivV : SchedRead; +def ReadVIDivX : SchedRead; +// 11.12. Vector Widening Integer Multiply Instructions +def ReadVIWMulV : SchedRead; +def ReadVIWMulX : SchedRead; +// 11.13. Vector Single-Width Integer Multiply-Add Instructions +def ReadVIMulAddV : SchedRead; +def ReadVIMulAddX : SchedRead; +// 11.14. Vector Widening Integer Multiply-Add Instructions +def ReadVIWMulAddV : SchedRead; +def ReadVIWMulAddX : SchedRead; +// 11.15. Vector Integer Merge Instructions +def ReadVIMergeV : SchedRead; +def ReadVIMergeX : SchedRead; +// 11.16. Vector Integer Move Instructions +def ReadVIMovV : SchedRead; +def ReadVIMovX : SchedRead; + +// 12. Vector Fixed-Point Arithmetic Instructions +// 12.1. Vector Single-Width Saturating Add and Subtract +def ReadVSALUV : SchedRead; +def ReadVSALUX : SchedRead; +// 12.2. Vector Single-Width Averaging Add and Subtract +def ReadVAALUV : SchedRead; +def ReadVAALUX : SchedRead; +// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation +def ReadVSMulV : SchedRead; +def ReadVSMulX : SchedRead; +// 12.4. Vector Single-Width Scaling Shift Instructions +def ReadVSShiftV : SchedRead; +def ReadVSShiftX : SchedRead; +// 12.5. Vector Narrowing Fixed-Point Clip Instructions +def ReadVNClipV : SchedRead; +def ReadVNClipX : SchedRead; + +// 13. Vector Floating-Point Instructions +// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions +def ReadVFALUV : SchedRead; +def ReadVFALUF : SchedRead; +// 13.3. Vector Widening Floating-Point Add/Subtract Instructions +def ReadVFWALUV : SchedRead; +def ReadVFWALUF : SchedRead; +// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions +def ReadVFMulV : SchedRead; +def ReadVFMulF : SchedRead; +def ReadVFDivV : SchedRead; +def ReadVFDivF : SchedRead; +// 13.5. Vector Widening Floating-Point Multiply +def ReadVFWMulV : SchedRead; +def ReadVFWMulF : SchedRead; +// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions +def ReadVFMulAddV : SchedRead; +def ReadVFMulAddF : SchedRead; +// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions +def ReadVFWMulAddV : SchedRead; +def ReadVFWMulAddF : SchedRead; +// 13.8. Vector Floating-Point Square-Root Instruction +def ReadVFSqrtV : SchedRead; +// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction +// 13.10. Vector Floating-Point Reciprocal Estimate Instruction +def ReadVFRecpV : SchedRead; +// 13.11. Vector Floating-Point MIN/MAX Instructions +// 13.13. Vector Floating-Point Compare Instructions +def ReadVFCmpV : SchedRead; +def ReadVFCmpF : SchedRead; +// 13.12. Vector Floating-Point Sign-Injection Instructions +def ReadVFSgnjV : SchedRead; +def ReadVFSgnjF : SchedRead; +// 13.14. Vector Floating-Point Classify Instruction +def ReadVFClassV : SchedRead; +// 13.15. Vector Floating-Point Merge Instruction +def ReadVFMergeV : SchedRead; +def ReadVFMergeF : SchedRead; +// 13.16. Vector Floating-Point Move Instruction +def ReadVFMovF : SchedRead; +// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions +def ReadVFCvtIToFV : SchedRead; +def ReadVFCvtFToIV : SchedRead; +// 13.18. Widening Floating-Point/Integer Type-Convert Instructions +def ReadVFWCvtIToFV : SchedRead; +def ReadVFWCvtFToIV : SchedRead; +def ReadVFWCvtFToFV : SchedRead; +// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions +def ReadVFNCvtIToFV : SchedRead; +def ReadVFNCvtFToIV : SchedRead; +def ReadVFNCvtFToFV : SchedRead; + +// 14. Vector Reduction Operations +// 14.1. Vector Single-Width Integer Reduction Instructions +def ReadVIRedV : SchedRead; +def ReadVIRedV0 : SchedRead; +// 14.2. Vector Widening Integer Reduction Instructions +def ReadVIWRedV : SchedRead; +def ReadVIWRedV0 : SchedRead; +// 14.3. Vector Single-Width Floating-Point Reduction Instructions +def ReadVFRedV : SchedRead; +def ReadVFRedV0 : SchedRead; +def ReadVFRedOV : SchedRead; +def ReadVFRedOV0 : SchedRead; +// 14.4. Vector Widening Floating-Point Reduction Instructions +def ReadVFWRedV : SchedRead; +def ReadVFWRedV0 : SchedRead; +def ReadVFWRedOV : SchedRead; +def ReadVFWRedOV0 : SchedRead; + +// 15. Vector Mask Instructions +// 15.1. Vector Mask-Register Logical Instructions +def ReadVMALUV : SchedRead; +// 15.2. Vector Mask Population Count +def ReadVMPopV : SchedRead; +// 15.3. Vector Find-First-Set Mask Bit +def ReadVMFFSV : SchedRead; +// 15.4. Vector Set-Before-First Mask Bit +// 15.5. Vector Set-Including-First Mask Bit +// 15.6. Vector Set-only-First Mask Bit +def ReadVMSFSV : SchedRead; +// 15.8. Vector Iota Instruction +def ReadVMIotV : SchedRead; + +// 16. Vector Permutation Instructions +// 16.1. Integer Scalar Move Instructions +def ReadVIMovVX : SchedRead; +def ReadVIMovXV : SchedRead; +def ReadVIMovXX : SchedRead; +// 16.2. Floating-Point Scalar Move Instructions +def ReadVFMovVF : SchedRead; +def ReadVFMovFV : SchedRead; +def ReadVFMovFX : SchedRead; +// 16.3. Vector Slide Instructions +def ReadVISlideV : SchedRead; +def ReadVISlideX : SchedRead; +def ReadVFSlideV : SchedRead; +def ReadVFSlideF : SchedRead; +// 16.4. Vector Register Gather Instructions +def ReadVGatherV : SchedRead; +def ReadVGatherX : SchedRead; +// 16.5. Vector Compress Instruction +def ReadVCompressV : SchedRead; +// 16.6. Whole Vector Register Move +def ReadVMov1V : SchedRead; +def ReadVMov2V : SchedRead; +def ReadVMov4V : SchedRead; +def ReadVMov8V : SchedRead; + +// Others +def ReadVMask : SchedRead; + +//===----------------------------------------------------------------------===// +/// Define default scheduler resources for V. + +multiclass UnsupportedSchedV { +let Unsupported = true in { + +// 7. Vector Loads and Stores +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// 12. Vector Integer Arithmetic Instructions +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// 13. Vector Fixed-Point Arithmetic Instructions +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// 14. Vector Floating-Point Instructions +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// 15. Vector Reduction Operations +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// 16. Vector Mask Instructions +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// 17. Vector Permutation Instructions +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// 7. Vector Loads and Stores +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// 12. Vector Integer Arithmetic Instructions +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// 13. Vector Fixed-Point Arithmetic Instructions +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// 14. Vector Floating-Point Instructions +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// 15. Vector Reduction Operations +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// 16. Vector Mask Instructions +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// 17. Vector Permutation Instructions +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// Others +def : ReadAdvance; + +} // Unsupported +} // UnsupportedSchedV