diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -75,7 +75,7 @@ // operand, so they have to be extended. If set to zero then the intrinsic // does not have any operand that must be extended. Intrinsic IntrinsicID = !cast(NAME); - bits<4> ExtendOperand = 0; + bits<4> SplatOperand = 0; } let TargetPrefix = "riscv" in { @@ -280,7 +280,7 @@ : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_any_ty, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } // For destination vector type is the same as first source vector (with mask). // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl) @@ -289,7 +289,7 @@ [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 3; + let SplatOperand = 3; } // For destination vector type is NOT the same as first source vector. // Input: (vector_in, vector_in/scalar_in, vl) @@ -297,7 +297,7 @@ : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } // For destination vector type is NOT the same as first source vector (with mask). // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl) @@ -306,7 +306,7 @@ [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 3; + let SplatOperand = 3; } // For binary operations with V0 as input. // Input: (vector_in, vector_in/scalar_in, V0, vl) @@ -316,7 +316,7 @@ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } // For binary operations with mask type output and V0 as input. // Output: (mask type output) @@ -327,7 +327,7 @@ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } // For binary operations with mask type output. // Output: (mask type output) @@ -336,7 +336,7 @@ : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], [llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } // For binary operations with mask type output without mask. // Output: (mask type output) @@ -345,7 +345,7 @@ : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], [llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } // For binary operations with mask type output with mask. // Output: (mask type output) @@ -356,7 +356,7 @@ llvm_anyvector_ty, llvm_any_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 3; + let SplatOperand = 3; } // For FP classify operations. // Output: (bit mask type output) @@ -380,7 +380,7 @@ : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_any_ty, llvm_anyint_ty], [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } // For Saturating binary operations with mask. // The destination vector type is the same as first source vector. @@ -390,7 +390,7 @@ [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic { - let ExtendOperand = 3; + let SplatOperand = 3; } // For Saturating binary operations. // The destination vector type is NOT the same as first source vector. @@ -399,7 +399,7 @@ : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty], [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } // For Saturating binary operations with mask. // The destination vector type is NOT the same as first source vector (with mask). @@ -409,7 +409,7 @@ [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic { - let ExtendOperand = 3; + let SplatOperand = 3; } class RISCVTernaryAAAXNoMask : Intrinsic<[llvm_anyvector_ty], @@ -426,28 +426,28 @@ [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } class RISCVTernaryAAXAMask : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } class RISCVTernaryWideNoMask : Intrinsic< [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty, llvm_anyint_ty], [IntrNoMem] >, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } class RISCVTernaryWideMask : Intrinsic< [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; + let SplatOperand = 2; } // For Reduction ternary operations. // For destination vector type is the same as first and third source vector. @@ -946,9 +946,7 @@ [IntrNoMem]>, RISCVVIntrinsic; def int_riscv_vmv_v_x : Intrinsic<[llvm_anyint_ty], [LLVMVectorElementType<0>, llvm_anyint_ty], - [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 1; - } + [IntrNoMem]>, RISCVVIntrinsic; def int_riscv_vfmv_v_f : Intrinsic<[llvm_anyfloat_ty], [LLVMVectorElementType<0>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic; @@ -959,9 +957,7 @@ def int_riscv_vmv_s_x : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMVectorElementType<0>, llvm_anyint_ty], - [IntrNoMem]>, RISCVVIntrinsic { - let ExtendOperand = 2; - } + [IntrNoMem]>, RISCVVIntrinsic; def int_riscv_vfmv_f_s : Intrinsic<[LLVMVectorElementType<0>], [llvm_anyfloat_ty], diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -97,6 +97,9 @@ // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand // for the VL value to be used for the operation. VFMV_V_F_VL, + // VMV_S_X_VL matches the semantics of vmv.s.x but includes an extra operand + // for the VL value to be used for the operation. + VMV_S_X_VL, // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign // extended from the vector element size. VMV_X_S, @@ -474,7 +477,7 @@ struct RISCVVIntrinsicInfo { unsigned IntrinsicID; - uint8_t ExtendedOperand; + uint8_t SplatOperand; }; using namespace RISCV; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -391,13 +391,12 @@ setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom); setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom); setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); - if (Subtarget.is64Bit()) { - setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); - setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); - } else { + if (!Subtarget.is64Bit()) { // We must custom-lower certain vXi64 operations on RV32 due to the vector // element type being illegal. setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom); @@ -2290,94 +2289,203 @@ return DAG.getNode(ISD::TRUNCATE, DL, EltVT, Elt0); } -SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, - SelectionDAG &DAG) const { - unsigned IntNo = cast(Op.getOperand(0))->getZExtValue(); +// Called by type legalization to handle splat of i64 on RV32. +// FIXME: We can optimize this when the type has sign or zero bits in one +// of the halves. +static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar, + SDValue VL, SelectionDAG &DAG) { + SDValue ThirtyTwoV = DAG.getConstant(32, DL, VT); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar, + DAG.getConstant(0, DL, MVT::i32)); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar, + DAG.getConstant(1, DL, MVT::i32)); + + // vmv.v.x vX, hi + // vsll.vx vX, vX, /*32*/ + // vmv.v.x vY, lo + // vsll.vx vY, vY, /*32*/ + // vsrl.vx vY, vY, /*32*/ + // vor.vv vX, vX, vY + MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorElementCount()); + SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL); + Lo = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Lo, VL); + Lo = DAG.getNode(RISCVISD::SHL_VL, DL, VT, Lo, ThirtyTwoV, Mask, VL); + Lo = DAG.getNode(RISCVISD::SRL_VL, DL, VT, Lo, ThirtyTwoV, Mask, VL); + + Hi = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Hi, VL); + Hi = DAG.getNode(RISCVISD::SHL_VL, DL, VT, Hi, ThirtyTwoV, Mask, VL); + + return DAG.getNode(RISCVISD::OR_VL, DL, VT, Lo, Hi, Mask, VL); +} + +// Some RVV intrinsics may claim that they want an integer operand to be +// promoted or expanded. +static SDValue lowerVectorIntrinsicSplats(SDValue Op, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + assert((Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || + Op.getOpcode() == ISD::INTRINSIC_W_CHAIN) && + "Unexpected opcode"); + + if (!Subtarget.hasStdExtV()) + return SDValue(); + + bool HasChain = Op.getOpcode() == ISD::INTRINSIC_W_CHAIN; + unsigned IntNo = Op.getConstantOperandVal(HasChain ? 1 : 0); SDLoc DL(Op); - if (Subtarget.hasStdExtV()) { - // Some RVV intrinsics may claim that they want an integer operand to be - // extended. - if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II = - RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo)) { - if (II->ExtendedOperand) { - assert(II->ExtendedOperand < Op.getNumOperands()); - SmallVector Operands(Op->op_begin(), Op->op_end()); - SDValue &ScalarOp = Operands[II->ExtendedOperand]; - EVT OpVT = ScalarOp.getValueType(); - if (OpVT == MVT::i8 || OpVT == MVT::i16 || - (OpVT == MVT::i32 && Subtarget.is64Bit())) { - // If the operand is a constant, sign extend to increase our chances - // of being able to use a .vi instruction. ANY_EXTEND would become a - // a zero extend and the simm5 check in isel would fail. - // FIXME: Should we ignore the upper bits in isel instead? - unsigned ExtOpc = isa(ScalarOp) ? ISD::SIGN_EXTEND - : ISD::ANY_EXTEND; - ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp); - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(), - Operands); - } - } + const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II = + RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo); + if (!II || !II->SplatOperand) + return SDValue(); + + unsigned SplatOp = II->SplatOperand + HasChain; + assert(SplatOp < Op.getNumOperands()); + + SmallVector Operands(Op->op_begin(), Op->op_end()); + SDValue &ScalarOp = Operands[SplatOp]; + MVT OpVT = ScalarOp.getSimpleValueType(); + MVT VT = Op.getSimpleValueType(); + MVT XLenVT = Subtarget.getXLenVT(); + + // If this isn't a scalar, or its type is XLenVT we're done. + if (!OpVT.isScalarInteger() || OpVT == XLenVT) + return SDValue(); + + // Simplest case is that the operand needs to be promoted to XLenVT. + if (OpVT.bitsLT(XLenVT)) { + // If the operand is a constant, sign extend to increase our chances + // of being able to use a .vi instruction. ANY_EXTEND would become a + // a zero extend and the simm5 check in isel would fail. + // FIXME: Should we ignore the upper bits in isel instead? + unsigned ExtOpc = isa(ScalarOp) ? ISD::SIGN_EXTEND + : ISD::ANY_EXTEND; + ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); + return DAG.getNode(Op->getOpcode(), DL, Op->getVTList(), Operands); + } + + // The more complex case is when the scalar is larger than XLenVT. + assert(XLenVT == MVT::i32 && OpVT == MVT::i64 && + VT.getVectorElementType() == MVT::i64 && + "Unexpected VTs!"); + + // If this is a sign-extended 32-bit constant, we can truncate it and rely + // on the instruction to sign-extend since SEW>XLEN. + if (auto *CVal = dyn_cast(ScalarOp)) { + if (isInt<32>(CVal->getSExtValue())) { + ScalarOp = DAG.getConstant(CVal->getSExtValue(), DL, MVT::i32); + return DAG.getNode(Op->getOpcode(), DL, Op->getVTList(), Operands); } } + // We need to convert the scalar to a splat vector. + // FIXME: Can we implicitly truncate the scalar if it is known to + // be sign extended? + // VL should be the last operand. + SDValue VL = Op.getOperand(Op.getNumOperands() - 1); + assert(VL.getValueType() == XLenVT); + ScalarOp = splatSplitI64WithVL(DL, VT, ScalarOp, VL, DAG); + return DAG.getNode(Op->getOpcode(), DL, Op->getVTList(), Operands); +} + +SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, + SelectionDAG &DAG) const { + unsigned IntNo = Op.getConstantOperandVal(0); + SDLoc DL(Op); + MVT XLenVT = Subtarget.getXLenVT(); + switch (IntNo) { default: - return SDValue(); // Don't custom lower most intrinsics. + break; // Don't custom lower most intrinsics. case Intrinsic::thread_pointer: { EVT PtrVT = getPointerTy(DAG.getDataLayout()); return DAG.getRegister(RISCV::X4, PtrVT); } case Intrinsic::riscv_vmv_x_s: - assert(Op.getValueType() == Subtarget.getXLenVT() && "Unexpected VT!"); + assert(Op.getValueType() == XLenVT && "Unexpected VT!"); return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(), Op.getOperand(1)); case Intrinsic::riscv_vmv_v_x: { - SDValue Scalar = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), - Op.getOperand(1)); - return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, Op.getValueType(), - Scalar, Op.getOperand(2)); + SDValue Scalar = Op.getOperand(1); + if (Scalar.getValueType().bitsLE(XLenVT)) { + unsigned ExtOpc = isa(Scalar) ? ISD::SIGN_EXTEND + : ISD::ANY_EXTEND; + Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); + return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, Op.getValueType(), + Scalar, Op.getOperand(2)); + } + + assert(Scalar.getValueType() == MVT::i64 && "Unexpected scalar VT!"); + + // If this is a sign-extended 32-bit constant, we can truncate it and rely + // on the instruction to sign-extend since SEW>XLEN. + if (auto *CVal = dyn_cast(Scalar)) { + if (isInt<32>(CVal->getSExtValue())) + return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, Op.getValueType(), + DAG.getConstant(CVal->getSExtValue(), DL, MVT::i32), + Op.getOperand(2)); + } + + // Otherwise use the more complicated splatting algorithm. + return splatSplitI64WithVL(DL, Op.getSimpleValueType(), Scalar, + Op.getOperand(2), DAG); } case Intrinsic::riscv_vfmv_v_f: return DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, Op.getValueType(), Op.getOperand(1), Op.getOperand(2)); + case Intrinsic::riscv_vmv_s_x: { + SDValue Scalar = Op.getOperand(2); + + if (Scalar.getValueType().bitsLE(XLenVT)) { + Scalar = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Scalar); + return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, Op.getValueType(), + Op.getOperand(1), Scalar, Op.getOperand(3)); + } + + assert(Scalar.getValueType() == MVT::i64 && "Unexpected scalar VT!"); + + // This is an i64 value that lives in two scalar registers. We have to + // insert this in a convoluted way. First we build vXi64 splat containing + // the/ two values that we assemble using some bit math. Next we'll use + // vid.v and vmseq to build a mask with bit 0 set. Then we'll use that mask + // to merge element 0 from our splat into the source vector. + // FIXME: This is probably not the best way to do this, but it is + // consistent with INSERT_VECTOR_ELT lowering so its a good starting + // point. + // vmv.v.x vX, hi + // vsll.vx vX, vX, /*32*/ + // vmv.v.x vY, lo + // vsll.vx vY, vY, /*32*/ + // vsrl.vx vY, vY, /*32*/ + // vor.vv vX, vX, vY + // + // vid.v vVid + // vmseq.vx mMask, vVid, 0 + // vmerge.vvm vDest, vSrc, vVal, mMask + MVT VT = Op.getSimpleValueType(); + SDValue Vec = Op.getOperand(1); + SDValue VL = Op.getOperand(3); + + SDValue SplattedVal = splatSplitI64WithVL(DL, VT, Scalar, VL, DAG); + SDValue SplattedIdx = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, + DAG.getConstant(0, DL, MVT::i32), VL); + + MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorElementCount()); + SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL); + SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL); + SDValue SelectCond = + DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, VID, SplattedIdx, + DAG.getCondCode(ISD::SETEQ), Mask, VL); + return DAG.getNode(RISCVISD::VSELECT_VL, DL, VT, + SelectCond, SplattedVal, Vec, VL); } + } + + return lowerVectorIntrinsicSplats(Op, DAG, Subtarget); } SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const { - unsigned IntNo = cast(Op.getOperand(1))->getZExtValue(); - SDLoc DL(Op); - - if (Subtarget.hasStdExtV()) { - // Some RVV intrinsics may claim that they want an integer operand to be - // extended. - if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II = - RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo)) { - if (II->ExtendedOperand) { - // The operands start from the second argument in INTRINSIC_W_CHAIN. - unsigned ExtendOp = II->ExtendedOperand + 1; - assert(ExtendOp < Op.getNumOperands()); - SmallVector Operands(Op->op_begin(), Op->op_end()); - SDValue &ScalarOp = Operands[ExtendOp]; - EVT OpVT = ScalarOp.getValueType(); - if (OpVT == MVT::i8 || OpVT == MVT::i16 || - (OpVT == MVT::i32 && Subtarget.is64Bit())) { - // If the operand is a constant, sign extend to increase our chances - // of being able to use a .vi instruction. ANY_EXTEND would become a - // a zero extend and the simm5 check in isel would fail. - // FIXME: Should we ignore the upper bits in isel instead? - unsigned ExtOpc = isa(ScalarOp) ? ISD::SIGN_EXTEND - : ISD::ANY_EXTEND; - ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp); - return DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, Op->getVTList(), - Operands); - } - } - } - } - - return SDValue(); // Don't custom lower most intrinsics. + return lowerVectorIntrinsicSplats(Op, DAG, Subtarget); } static MVT getLMUL1VT(MVT VT) { @@ -5734,6 +5842,7 @@ NODE_NAME_CASE(SHFLI) NODE_NAME_CASE(VMV_V_X_VL) NODE_NAME_CASE(VFMV_V_F_VL) + NODE_NAME_CASE(VMV_S_X_VL) NODE_NAME_CASE(VMV_X_S) NODE_NAME_CASE(SPLAT_VECTOR_I64) NODE_NAME_CASE(READ_VLENB) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -17,6 +17,11 @@ def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S", SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>, SDTCisInt<1>]>>; +def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", + SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, + SDTCisSameAs<0, 1>, + SDTCisVT<2, XLenVT>, + SDTCisVT<3, XLenVT>]>>; def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB", SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>; @@ -394,7 +399,7 @@ def RISCVVIntrinsicsTable : GenericTable { let FilterClass = "RISCVVIntrinsic"; let CppTypeName = "RISCVVIntrinsicInfo"; - let Fields = ["IntrinsicID", "ExtendOperand"]; + let Fields = ["IntrinsicID", "SplatOperand"]; let PrimaryKey = ["IntrinsicID"]; let PrimaryKeyName = "getRISCVVIntrinsicInfo"; } @@ -4268,8 +4273,8 @@ foreach vti = AllIntegerVectors in { def : Pat<(riscv_vmv_x_s (vti.Vector vti.RegClass:$rs2)), (!cast("PseudoVMV_X_S_" # vti.LMul.MX) $rs2, vti.SEW)>; - def : Pat<(vti.Vector (int_riscv_vmv_s_x (vti.Vector vti.RegClass:$rs1), - GPR:$rs2, (XLenVT (VLOp GPR:$vl)))), + def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$rs1), + GPR:$rs2, (XLenVT (VLOp GPR:$vl)))), (!cast("PseudoVMV_S_X_" # vti.LMul.MX) (vti.Vector $rs1), $rs2, GPR:$vl, vti.SEW)>; } diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll @@ -796,6 +796,183 @@ ret %a } +declare @llvm.riscv.vaadd.nxv1i64.nxv1i64( + , + , + i32); + +define @intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.nxv1i64.nxv1i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64( + , + , + , + , + i32); + +define @intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaadd.nxv2i64.nxv2i64( + , + , + i32); + +define @intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.nxv2i64.nxv2i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaadd.mask.nxv2i64.nxv2i64( + , + , + , + , + i32); + +define @intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.mask.nxv2i64.nxv2i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaadd.nxv4i64.nxv4i64( + , + , + i32); + +define @intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.nxv4i64.nxv4i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaadd.mask.nxv4i64.nxv4i64( + , + , + , + , + i32); + +define @intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.mask.nxv4i64.nxv4i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaadd.nxv8i64.nxv8i64( + , + , + i32); + +define @intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.nxv8i64.nxv8i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64( + , + , + , + , + i32); + +define @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vaadd.nxv1i8.i8( , i8, @@ -1587,3 +1764,245 @@ ret %a } + +declare @llvm.riscv.vaadd.nxv1i64.i64( + , + i64, + i32); + +define @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vaadd.vv v8, v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.nxv1i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaadd.mask.nxv1i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaadd.nxv2i64.i64( + , + i64, + i32); + +define @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vaadd.vv v8, v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.nxv2i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaadd.mask.nxv2i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v10, v26, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaadd.nxv4i64.i64( + , + i64, + i32); + +define @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vaadd.vv v8, v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.nxv4i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaadd.mask.nxv4i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vsrl.vx v16, v16, a1 +; CHECK-NEXT: vor.vv v28, v16, v28 +; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v12, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaadd.nxv8i64.i64( + , + i64, + i32); + +define @intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vaadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.nxv8i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaadd.mask.nxv8i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrrs a3, vlenb, zero +; CHECK-NEXT: sub sp, sp, a3 +; CHECK-NEXT: vs1r.v v0, (sp) # Unknown-size Folded Spill +; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v24, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v0, v24, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v24, v24, v0 +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vl1re8.v v0, (sp) # Unknown-size Folded Reload +; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: csrrs a0, vlenb, zero +; CHECK-NEXT: add sp, sp, a0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaadd.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll @@ -796,6 +796,183 @@ ret %a } +declare @llvm.riscv.vaaddu.nxv1i64.nxv1i64( + , + , + i32); + +define @intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.nxv1i64.nxv1i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64( + , + , + , + , + i32); + +define @intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaaddu.nxv2i64.nxv2i64( + , + , + i32); + +define @intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.nxv2i64.nxv2i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaaddu.mask.nxv2i64.nxv2i64( + , + , + , + , + i32); + +define @intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.mask.nxv2i64.nxv2i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaaddu.nxv4i64.nxv4i64( + , + , + i32); + +define @intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.nxv4i64.nxv4i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaaddu.mask.nxv4i64.nxv4i64( + , + , + , + , + i32); + +define @intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.mask.nxv4i64.nxv4i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaaddu.nxv8i64.nxv8i64( + , + , + i32); + +define @intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.nxv8i64.nxv8i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64( + , + , + , + , + i32); + +define @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vaaddu.nxv1i8.i8( , i8, @@ -1587,3 +1764,245 @@ ret %a } + +declare @llvm.riscv.vaaddu.nxv1i64.i64( + , + i64, + i32); + +define @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vaaddu.vv v8, v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.nxv1i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaaddu.mask.nxv1i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaaddu.nxv2i64.i64( + , + i64, + i32); + +define @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vaaddu.vv v8, v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.nxv2i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaaddu.mask.nxv2i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v10, v26, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaaddu.nxv4i64.i64( + , + i64, + i32); + +define @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vaaddu.vv v8, v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.nxv4i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaaddu.mask.nxv4i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vsrl.vx v16, v16, a1 +; CHECK-NEXT: vor.vv v28, v16, v28 +; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v12, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vaaddu.nxv8i64.i64( + , + i64, + i32); + +define @intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.nxv8i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vaaddu.mask.nxv8i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrrs a3, vlenb, zero +; CHECK-NEXT: sub sp, sp, a3 +; CHECK-NEXT: vs1r.v v0, (sp) # Unknown-size Folded Spill +; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v24, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v0, v24, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v24, v24, v0 +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vl1re8.v v0, (sp) # Unknown-size Folded Reload +; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: csrrs a0, vlenb, zero +; CHECK-NEXT: add sp, sp, a0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vaaddu.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll @@ -397,6 +397,94 @@ ret %a } +declare @llvm.riscv.vadc.nxv1i64.nxv1i64( + , + , + , + i32); + +define @intrinsic_vadc_vvm_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv1i64.nxv1i64( + %0, + %1, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vadc.nxv2i64.nxv2i64( + , + , + , + i32); + +define @intrinsic_vadc_vvm_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv2i64.nxv2i64( + %0, + %1, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vadc.nxv4i64.nxv4i64( + , + , + , + i32); + +define @intrinsic_vadc_vvm_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv4i64.nxv4i64( + %0, + %1, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vadc.nxv8i64.nxv8i64( + , + , + , + i32); + +define @intrinsic_vadc_vvm_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv8i64.nxv8i64( + %0, + %1, + %2, + i32 %3) + + ret %a +} + declare @llvm.riscv.vadc.nxv1i8.i8( , i8, @@ -793,6 +881,122 @@ ret %a } +declare @llvm.riscv.vadc.nxv1i64.i64( + , + i64, + , + i32); + +define @intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64( %0, i64 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vadc.vvm v8, v8, v25, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv1i64.i64( + %0, + i64 %1, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vadc.nxv2i64.i64( + , + i64, + , + i32); + +define @intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64( %0, i64 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vadc.vvm v8, v8, v26, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv2i64.i64( + %0, + i64 %1, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vadc.nxv4i64.i64( + , + i64, + , + i32); + +define @intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64( %0, i64 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vadc.vvm v8, v8, v28, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv4i64.i64( + %0, + i64 %1, + %2, + i32 %3) + + ret %a +} + +declare @llvm.riscv.vadc.nxv8i64.i64( + , + i64, + , + i32); + +define @intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64( %0, i64 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv8i64.i64( + %0, + i64 %1, + %2, + i32 %3) + + ret %a +} + define @intrinsic_vadc_vim_nxv1i8_nxv1i8_i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry @@ -1080,3 +1284,67 @@ ret %a } + +define @intrinsic_vadc_vim_nxv1i64_nxv1i64_i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv1i64.i64( + %0, + i64 9, + %1, + i32 %2) + + ret %a +} + +define @intrinsic_vadc_vim_nxv2i64_nxv2i64_i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv2i64.i64( + %0, + i64 -9, + %1, + i32 %2) + + ret %a +} + +define @intrinsic_vadc_vim_nxv4i64_nxv4i64_i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv4i64.i64( + %0, + i64 9, + %1, + i32 %2) + + ret %a +} + +define @intrinsic_vadc_vim_nxv8i64_nxv8i64_i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadc.nxv8i64.i64( + %0, + i64 -9, + %1, + i32 %2) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll @@ -796,6 +796,183 @@ ret %a } +declare @llvm.riscv.vadd.nxv1i64.nxv1i64( + , + , + i32); + +define @intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv1i64.nxv1i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vadd.mask.nxv1i64.nxv1i64( + , + , + , + , + i32); + +define @intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv1i64.nxv1i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vadd.nxv2i64.nxv2i64( + , + , + i32); + +define @intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv2i64.nxv2i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vadd.mask.nxv2i64.nxv2i64( + , + , + , + , + i32); + +define @intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv2i64.nxv2i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vadd.nxv4i64.nxv4i64( + , + , + i32); + +define @intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv4i64.nxv4i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vadd.mask.nxv4i64.nxv4i64( + , + , + , + , + i32); + +define @intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv4i64.nxv4i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vadd.nxv8i64.nxv8i64( + , + , + i32); + +define @intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv8i64.nxv8i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vadd.mask.nxv8i64.nxv8i64( + , + , + , + , + i32); + +define @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv8i64.nxv8i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vadd.nxv1i8.i8( , i8, @@ -1588,6 +1765,248 @@ ret %a } +declare @llvm.riscv.vadd.nxv1i64.i64( + , + i64, + i32); + +define @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vadd.vv v8, v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv1i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vadd.mask.nxv1i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vadd.nxv2i64.i64( + , + i64, + i32); + +define @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vadd.vv v8, v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv2i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vadd.mask.nxv2i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu +; CHECK-NEXT: vadd.vv v8, v10, v26, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vadd.nxv4i64.i64( + , + i64, + i32); + +define @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vadd.vv v8, v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv4i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vadd.mask.nxv4i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vsrl.vx v16, v16, a1 +; CHECK-NEXT: vor.vv v28, v16, v28 +; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu +; CHECK-NEXT: vadd.vv v8, v12, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vadd.nxv8i64.i64( + , + i64, + i32); + +define @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv8i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vadd.mask.nxv8i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrrs a3, vlenb, zero +; CHECK-NEXT: sub sp, sp, a3 +; CHECK-NEXT: vs1r.v v0, (sp) # Unknown-size Folded Spill +; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v24, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v0, v24, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v24, v24, v0 +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vl1re8.v v0, (sp) # Unknown-size Folded Reload +; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: csrrs a0, vlenb, zero +; CHECK-NEXT: add sp, sp, a0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + define @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry @@ -2163,3 +2582,131 @@ ret %a } + +define @intrinsic_vadd_vi_nxv1i64_nxv1i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv1i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv1i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vadd_vi_nxv2i64_nxv2i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv2i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv2i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vadd_vi_nxv4i64_nxv4i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv4i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv4i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vadd_vi_nxv8i64_nxv8i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.nxv8i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vadd.mask.nxv8i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll @@ -796,6 +796,183 @@ ret %a } +declare @llvm.riscv.vand.nxv1i64.nxv1i64( + , + , + i32); + +define @intrinsic_vand_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv1i64.nxv1i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vand.mask.nxv1i64.nxv1i64( + , + , + , + , + i32); + +define @intrinsic_vand_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv1i64.nxv1i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vand.nxv2i64.nxv2i64( + , + , + i32); + +define @intrinsic_vand_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv2i64.nxv2i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vand.mask.nxv2i64.nxv2i64( + , + , + , + , + i32); + +define @intrinsic_vand_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vand.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv2i64.nxv2i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vand.nxv4i64.nxv4i64( + , + , + i32); + +define @intrinsic_vand_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv4i64.nxv4i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vand.mask.nxv4i64.nxv4i64( + , + , + , + , + i32); + +define @intrinsic_vand_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vand.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv4i64.nxv4i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vand.nxv8i64.nxv8i64( + , + , + i32); + +define @intrinsic_vand_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv8i64.nxv8i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vand.mask.nxv8i64.nxv8i64( + , + , + , + , + i32); + +define @intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vand.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv8i64.nxv8i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vand.nxv1i8.i8( , i8, @@ -1588,6 +1765,248 @@ ret %a } +declare @llvm.riscv.vand.nxv1i64.i64( + , + i64, + i32); + +define @intrinsic_vand_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vand.vv v8, v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv1i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vand.mask.nxv1i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vand.nxv2i64.i64( + , + i64, + i32); + +define @intrinsic_vand_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vand.vv v8, v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv2i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vand.mask.nxv2i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu +; CHECK-NEXT: vand.vv v8, v10, v26, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vand.nxv4i64.i64( + , + i64, + i32); + +define @intrinsic_vand_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vand.vv v8, v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv4i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vand.mask.nxv4i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vsrl.vx v16, v16, a1 +; CHECK-NEXT: vor.vv v28, v16, v28 +; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu +; CHECK-NEXT: vand.vv v8, v12, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vand.nxv8i64.i64( + , + i64, + i32); + +define @intrinsic_vand_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv8i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vand.mask.nxv8i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrrs a3, vlenb, zero +; CHECK-NEXT: sub sp, sp, a3 +; CHECK-NEXT: vs1r.v v0, (sp) # Unknown-size Folded Spill +; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v24, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v0, v24, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v24, v24, v0 +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vl1re8.v v0, (sp) # Unknown-size Folded Reload +; CHECK-NEXT: vand.vv v8, v16, v24, v0.t +; CHECK-NEXT: csrrs a0, vlenb, zero +; CHECK-NEXT: add sp, sp, a0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + define @intrinsic_vand_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vand_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry @@ -2163,3 +2582,131 @@ ret %a } + +define @intrinsic_vand_vi_nxv1i64_nxv1i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv1i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vand_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv1i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vand_vi_nxv2i64_nxv2i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv2i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vand_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vand.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv2i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vand_vi_nxv4i64_nxv4i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv4i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vand_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vand.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv4i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vand_vi_nxv8i64_nxv8i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.nxv8i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vand_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vand.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vand.mask.nxv8i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll @@ -796,6 +796,183 @@ ret %a } +declare @llvm.riscv.vasub.nxv1i64.nxv1i64( + , + , + i32); + +define @intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.nxv1i64.nxv1i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasub.mask.nxv1i64.nxv1i64( + , + , + , + , + i32); + +define @intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.mask.nxv1i64.nxv1i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasub.nxv2i64.nxv2i64( + , + , + i32); + +define @intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.nxv2i64.nxv2i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasub.mask.nxv2i64.nxv2i64( + , + , + , + , + i32); + +define @intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.mask.nxv2i64.nxv2i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasub.nxv4i64.nxv4i64( + , + , + i32); + +define @intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.nxv4i64.nxv4i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasub.mask.nxv4i64.nxv4i64( + , + , + , + , + i32); + +define @intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.mask.nxv4i64.nxv4i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasub.nxv8i64.nxv8i64( + , + , + i32); + +define @intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.nxv8i64.nxv8i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasub.mask.nxv8i64.nxv8i64( + , + , + , + , + i32); + +define @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.mask.nxv8i64.nxv8i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vasub.nxv1i8.i8( , i8, @@ -1587,3 +1764,245 @@ ret %a } + +declare @llvm.riscv.vasub.nxv1i64.i64( + , + i64, + i32); + +define @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vasub.vv v8, v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.nxv1i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasub.mask.nxv1i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasub.nxv2i64.i64( + , + i64, + i32); + +define @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vasub.vv v8, v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.nxv2i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasub.mask.nxv2i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu +; CHECK-NEXT: vasub.vv v8, v10, v26, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasub.nxv4i64.i64( + , + i64, + i32); + +define @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vasub.vv v8, v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.nxv4i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasub.mask.nxv4i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vsrl.vx v16, v16, a1 +; CHECK-NEXT: vor.vv v28, v16, v28 +; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu +; CHECK-NEXT: vasub.vv v8, v12, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasub.nxv8i64.i64( + , + i64, + i32); + +define @intrinsic_vasub_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vasub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.nxv8i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasub.mask.nxv8i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrrs a3, vlenb, zero +; CHECK-NEXT: sub sp, sp, a3 +; CHECK-NEXT: vs1r.v v0, (sp) # Unknown-size Folded Spill +; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v24, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v0, v24, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v24, v24, v0 +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vl1re8.v v0, (sp) # Unknown-size Folded Reload +; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t +; CHECK-NEXT: csrrs a0, vlenb, zero +; CHECK-NEXT: add sp, sp, a0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasub.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll @@ -796,6 +796,183 @@ ret %a } +declare @llvm.riscv.vasubu.nxv1i64.nxv1i64( + , + , + i32); + +define @intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.nxv1i64.nxv1i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasubu.mask.nxv1i64.nxv1i64( + , + , + , + , + i32); + +define @intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.mask.nxv1i64.nxv1i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasubu.nxv2i64.nxv2i64( + , + , + i32); + +define @intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.nxv2i64.nxv2i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasubu.mask.nxv2i64.nxv2i64( + , + , + , + , + i32); + +define @intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.mask.nxv2i64.nxv2i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasubu.nxv4i64.nxv4i64( + , + , + i32); + +define @intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.nxv4i64.nxv4i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasubu.mask.nxv4i64.nxv4i64( + , + , + , + , + i32); + +define @intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.mask.nxv4i64.nxv4i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasubu.nxv8i64.nxv8i64( + , + , + i32); + +define @intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.nxv8i64.nxv8i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64( + , + , + , + , + i32); + +define @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vasubu.nxv1i8.i8( , i8, @@ -1587,3 +1764,245 @@ ret %a } + +declare @llvm.riscv.vasubu.nxv1i64.i64( + , + i64, + i32); + +define @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vasubu.vv v8, v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.nxv1i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasubu.mask.nxv1i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasubu.nxv2i64.i64( + , + i64, + i32); + +define @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vasubu.vv v8, v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.nxv2i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasubu.mask.nxv2i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v10, v26, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasubu.nxv4i64.i64( + , + i64, + i32); + +define @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vasubu.vv v8, v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.nxv4i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasubu.mask.nxv4i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vsrl.vx v16, v16, a1 +; CHECK-NEXT: vor.vv v28, v16, v28 +; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v12, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vasubu.nxv8i64.i64( + , + i64, + i32); + +define @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vasubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.nxv8i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vasubu.mask.nxv8i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrrs a3, vlenb, zero +; CHECK-NEXT: sub sp, sp, a3 +; CHECK-NEXT: vs1r.v v0, (sp) # Unknown-size Folded Spill +; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v24, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v0, v24, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v24, v24, v0 +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vl1re8.v v0, (sp) # Unknown-size Folded Reload +; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: csrrs a0, vlenb, zero +; CHECK-NEXT: add sp, sp, a0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vasubu.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll @@ -234,3 +234,91 @@ %a = call @llvm.riscv.vmv.s.x.nxv16i32( %0, i32 %1, i32 %2) ret %a } + +declare @llvm.riscv.vmv.s.x.nxv1i64(, i64, i32); + +define @intrinsic_vmv.s.x_x_nxv1i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vid.v v26 +; CHECK-NEXT: vmseq.vi v0, v26, 0 +; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmv.s.x.nxv1i64( %0, i64 %1, i32 %2) + ret %a +} + +declare @llvm.riscv.vmv.s.x.nxv2i64(, i64, i32); + +define @intrinsic_vmv.s.x_x_nxv2i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vid.v v28 +; CHECK-NEXT: vmseq.vi v0, v28, 0 +; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmv.s.x.nxv2i64( %0, i64 %1, i32 %2) + ret %a +} + +declare @llvm.riscv.vmv.s.x.nxv4i64(, i64, i32); + +define @intrinsic_vmv.s.x_x_nxv4i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vmseq.vi v0, v12, 0 +; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmv.s.x.nxv4i64( %0, i64 %1, i32 %2) + ret %a +} + +declare @llvm.riscv.vmv.s.x.nxv8i64(, i64, i32); + +define @intrinsic_vmv.s.x_x_nxv8i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vid.v v24 +; CHECK-NEXT: vmseq.vi v0, v24, 0 +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmv.s.x.nxv8i64( %0, i64 %1, i32 %2) + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll @@ -325,6 +325,102 @@ ret %a } +declare @llvm.riscv.vmv.v.x.nxv1i64( + i64, + i32); + +define @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v8, v26, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vmv.v.x.nxv1i64( + i64 %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vmv.v.x.nxv2i64( + i64, + i32); + +define @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v8, v28, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vmv.v.x.nxv2i64( + i64 %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vmv.v.x.nxv4i64( + i64, + i32); + +define @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vor.vv v8, v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vmv.v.x.nxv4i64( + i64 %0, + i32 %1) + + ret %a +} + +declare @llvm.riscv.vmv.v.x.nxv8i64( + i64, + i32); + +define @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vsrl.vx v16, v16, a1 +; CHECK-NEXT: vor.vv v8, v16, v8 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vmv.v.x.nxv8i64( + i64 %0, + i32 %1) + + ret %a +} + define @intrinsic_vmv.v.x_i_nxv1i8(i32 %0) nounwind { ; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8: ; CHECK: # %bb.0: # %entry @@ -576,3 +672,59 @@ ret %a } + +define @intrinsic_vmv.v.x_i_nxv1i64(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vmv.v.x.nxv1i64( + i64 9, + i32 %0) + + ret %a +} + +define @intrinsic_vmv.v.x_i_nxv2i64(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vmv.v.x.nxv2i64( + i64 9, + i32 %0) + + ret %a +} + +define @intrinsic_vmv.v.x_i_nxv4i64(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vmv.v.x.nxv4i64( + i64 9, + i32 %0) + + ret %a +} + +define @intrinsic_vmv.v.x_i_nxv8i64(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vmv.v.x.nxv8i64( + i64 9, + i32 %0) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll @@ -496,6 +496,186 @@ ret %a } +declare @llvm.riscv.vnsra.nxv1i32.nxv1i64.nxv1i32( + , + , + i32); + +define @intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv1i32.nxv1i64.nxv1i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.nxv1i32( + , + , + , + , + i32); + +define @intrinsic_vnsra_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.nxv1i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32( + , + , + i32); + +define @intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.nxv2i32( + , + , + , + , + i32); + +define @intrinsic_vnsra_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnsra.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.nxv2i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32( + , + , + i32); + +define @intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnsra.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.nxv4i32( + , + , + , + , + i32); + +define @intrinsic_vnsra_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.nxv4i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32( + , + , + i32); + +define @intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnsra.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.nxv8i32( + , + , + , + , + i32); + +define @intrinsic_vnsra_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.nxv8i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( , i8, @@ -991,6 +1171,186 @@ ret %a } +declare @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32( + , + i32, + i32); + +define @intrinsic_vnsra_wx_nxv1i32_nxv1i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vnsra_mask_wx_nxv1i32_nxv1i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32( + , + i32, + i32); + +define @intrinsic_vnsra_wx_nxv2i32_nxv2i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vnsra_mask_wx_nxv2i32_nxv2i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32( + , + i32, + i32); + +define @intrinsic_vnsra_wx_nxv4i32_nxv4i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vnsra.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vnsra_mask_wx_nxv4i32_nxv4i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32( + , + i32, + i32); + +define @intrinsic_vnsra_wx_nxv8i32_nxv8i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vnsra.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vnsra_mask_wx_nxv8i32_nxv8i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + define @intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8( %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry @@ -1353,3 +1713,135 @@ ret %a } + +define @intrinsic_vnsra_wi_nxv1i32_nxv1i64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32( + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vnsra_mask_wi_nxv1i32_nxv1i64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vnsra_wi_nxv2i32_nxv2i64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32( + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vnsra_mask_wi_nxv2i32_nxv2i64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vnsra_wi_nxv4i32_nxv4i64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnsra.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32( + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vnsra_mask_wi_nxv4i32_nxv4i64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vnsra_wi_nxv8i32_nxv8i64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnsra.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32( + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vnsra_mask_wi_nxv8i32_nxv8i64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll @@ -496,6 +496,186 @@ ret %a } +declare @llvm.riscv.vnsrl.nxv1i32.nxv1i64.nxv1i32( + , + , + i32); + +define @intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv1i32.nxv1i64.nxv1i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.nxv1i32( + , + , + , + , + i32); + +define @intrinsic_vnsrl_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.nxv1i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32( + , + , + i32); + +define @intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.nxv2i32( + , + , + , + , + i32); + +define @intrinsic_vnsrl_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.nxv2i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32( + , + , + i32); + +define @intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnsrl.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.nxv4i32( + , + , + , + , + i32); + +define @intrinsic_vnsrl_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.nxv4i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32( + , + , + i32); + +define @intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnsrl.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.nxv8i32( + , + , + , + , + i32); + +define @intrinsic_vnsrl_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.nxv8i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( , i8, @@ -991,6 +1171,186 @@ ret %a } +declare @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32( + , + i32, + i32); + +define @intrinsic_vnsrl_wx_nxv1i32_nxv1i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vnsrl_mask_wx_nxv1i32_nxv1i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32( + , + i32, + i32); + +define @intrinsic_vnsrl_wx_nxv2i32_nxv2i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vnsrl_mask_wx_nxv2i32_nxv2i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32( + , + i32, + i32); + +define @intrinsic_vnsrl_wx_nxv4i32_nxv4i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vnsrl.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vnsrl_mask_wx_nxv4i32_nxv4i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32( + , + i32, + i32); + +define @intrinsic_vnsrl_wx_nxv8i32_nxv8i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vnsrl.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vnsrl_mask_wx_nxv8i32_nxv8i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + define @intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8( %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry @@ -1353,3 +1713,135 @@ ret %a } + +define @intrinsic_vnsrl_wi_nxv1i32_nxv1i64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32( + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vnsrl_mask_wi_nxv1i32_nxv1i64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vnsrl_wi_nxv2i32_nxv2i64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32( + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vnsrl_mask_wi_nxv2i32_nxv2i64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vnsrl_wi_nxv4i32_nxv4i64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnsrl.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32( + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vnsrl_mask_wi_nxv4i32_nxv4i64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vnsrl_wi_nxv8i32_nxv8i64_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnsrl.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32( + %0, + i32 9, + i32 %1) + + ret %a +} + +define @intrinsic_vnsrl_mask_wi_nxv8i32_nxv8i64_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32( + %0, + %1, + i32 9, + %2, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll @@ -796,6 +796,183 @@ ret %a } +declare @llvm.riscv.vssra.nxv1i64.nxv1i64( + , + , + i32); + +define @intrinsic_vssra_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv1i64.nxv1i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssra.mask.nxv1i64.nxv1i64( + , + , + , + , + i32); + +define @intrinsic_vssra_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv1i64.nxv1i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssra.nxv2i64.nxv2i64( + , + , + i32); + +define @intrinsic_vssra_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv2i64.nxv2i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssra.mask.nxv2i64.nxv2i64( + , + , + , + , + i32); + +define @intrinsic_vssra_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv2i64.nxv2i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssra.nxv4i64.nxv4i64( + , + , + i32); + +define @intrinsic_vssra_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv4i64.nxv4i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssra.mask.nxv4i64.nxv4i64( + , + , + , + , + i32); + +define @intrinsic_vssra_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv4i64.nxv4i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssra.nxv8i64.nxv8i64( + , + , + i32); + +define @intrinsic_vssra_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv8i64.nxv8i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssra.mask.nxv8i64.nxv8i64( + , + , + , + , + i32); + +define @intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv8i64.nxv8i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vssra.nxv1i8.i8( , i8, @@ -1588,6 +1765,248 @@ ret %a } +declare @llvm.riscv.vssra.nxv1i64.i64( + , + i64, + i32); + +define @intrinsic_vssra_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vssra.vv v8, v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv1i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssra.mask.nxv1i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vssra_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssra.nxv2i64.i64( + , + i64, + i32); + +define @intrinsic_vssra_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vssra.vv v8, v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv2i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssra.mask.nxv2i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vssra_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu +; CHECK-NEXT: vssra.vv v8, v10, v26, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssra.nxv4i64.i64( + , + i64, + i32); + +define @intrinsic_vssra_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vssra.vv v8, v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv4i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssra.mask.nxv4i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vssra_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vsrl.vx v16, v16, a1 +; CHECK-NEXT: vor.vv v28, v16, v28 +; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu +; CHECK-NEXT: vssra.vv v8, v12, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssra.nxv8i64.i64( + , + i64, + i32); + +define @intrinsic_vssra_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vssra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv8i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssra.mask.nxv8i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vssra_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrrs a3, vlenb, zero +; CHECK-NEXT: sub sp, sp, a3 +; CHECK-NEXT: vs1r.v v0, (sp) # Unknown-size Folded Spill +; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v24, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v0, v24, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v24, v24, v0 +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vl1re8.v v0, (sp) # Unknown-size Folded Reload +; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t +; CHECK-NEXT: csrrs a0, vlenb, zero +; CHECK-NEXT: add sp, sp, a0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + define @intrinsic_vssra_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vssra_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry @@ -2163,3 +2582,131 @@ ret %a } + +define @intrinsic_vssra_vi_nxv1i64_nxv1i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv1i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv1i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vssra_vi_nxv2i64_nxv2i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv2i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv2i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vssra_vi_nxv4i64_nxv4i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv4i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv4i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vssra_vi_nxv8i64_nxv8i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.nxv8i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssra.mask.nxv8i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll @@ -796,6 +796,183 @@ ret %a } +declare @llvm.riscv.vssrl.nxv1i64.nxv1i64( + , + , + i32); + +define @intrinsic_vssrl_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv1i64.nxv1i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64( + , + , + , + , + i32); + +define @intrinsic_vssrl_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssrl.nxv2i64.nxv2i64( + , + , + i32); + +define @intrinsic_vssrl_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv2i64.nxv2i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64( + , + , + , + , + i32); + +define @intrinsic_vssrl_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssrl.nxv4i64.nxv4i64( + , + , + i32); + +define @intrinsic_vssrl_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv4i64.nxv4i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64( + , + , + , + , + i32); + +define @intrinsic_vssrl_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssrl.nxv8i64.nxv8i64( + , + , + i32); + +define @intrinsic_vssrl_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv8i64.nxv8i64( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64( + , + , + , + , + i32); + +define @intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vssrl.nxv1i8.i8( , i8, @@ -1588,6 +1765,248 @@ ret %a } +declare @llvm.riscv.vssrl.nxv1i64.i64( + , + i64, + i32); + +define @intrinsic_vssrl_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vssrl.vv v8, v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv1i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssrl.mask.nxv1i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v25, v25, a1 +; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vsrl.vx v26, v26, a1 +; CHECK-NEXT: vor.vv v25, v26, v25 +; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv1i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssrl.nxv2i64.i64( + , + i64, + i32); + +define @intrinsic_vssrl_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vssrl.vv v8, v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv2i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssrl.mask.nxv2i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v26, v26, a1 +; CHECK-NEXT: vmv.v.x v28, a0 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vsrl.vx v28, v28, a1 +; CHECK-NEXT: vor.vv v26, v28, v26 +; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v10, v26, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv2i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssrl.nxv4i64.i64( + , + i64, + i32); + +define @intrinsic_vssrl_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vssrl.vv v8, v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv4i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssrl.mask.nxv4i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v28, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v28, v28, a1 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vsrl.vx v16, v16, a1 +; CHECK-NEXT: vor.vv v28, v16, v28 +; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v12, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv4i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vssrl.nxv8i64.i64( + , + i64, + i32); + +define @intrinsic_vssrl_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v16, v16, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vssrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv8i64.i64( + %0, + i64 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vssrl.mask.nxv8i64.i64( + , + , + i64, + , + i32); + +define @intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: csrrs a3, vlenb, zero +; CHECK-NEXT: sub sp, sp, a3 +; CHECK-NEXT: vs1r.v v0, (sp) # Unknown-size Folded Spill +; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v24, a1 +; CHECK-NEXT: addi a1, zero, 32 +; CHECK-NEXT: vsll.vx v0, v24, a1 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vsll.vx v24, v24, a1 +; CHECK-NEXT: vsrl.vx v24, v24, a1 +; CHECK-NEXT: vor.vv v24, v24, v0 +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vl1re8.v v0, (sp) # Unknown-size Folded Reload +; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: csrrs a0, vlenb, zero +; CHECK-NEXT: add sp, sp, a0 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv8i64.i64( + %0, + %1, + i64 %2, + %3, + i32 %4) + + ret %a +} + define @intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry @@ -2163,3 +2582,131 @@ ret %a } + +define @intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv1i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv1i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv2i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv2i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv4i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv4i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} + +define @intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.nxv8i64.i64( + %0, + i64 9, + i32 %1) + + ret %a +} + +define @intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vssrl.mask.nxv8i64.i64( + %0, + %1, + i64 9, + %2, + i32 %3) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll @@ -496,6 +496,186 @@ ret %a } +declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32( + , + , + i32); + +define @intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwadd.mask.nxv1i64.nxv1i32.nxv1i32( + , + , + , + , + i32); + +define @intrinsic_vwadd_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.mask.nxv1i64.nxv1i32.nxv1i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwadd.nxv2i64.nxv2i32.nxv2i32( + , + , + i32); + +define @intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwadd.mask.nxv2i64.nxv2i32.nxv2i32( + , + , + , + , + i32); + +define @intrinsic_vwadd_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.mask.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwadd.nxv4i64.nxv4i32.nxv4i32( + , + , + i32); + +define @intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwadd.mask.nxv4i64.nxv4i32.nxv4i32( + , + , + , + , + i32); + +define @intrinsic_vwadd_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.mask.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwadd.nxv8i64.nxv8i32.nxv8i32( + , + , + i32); + +define @intrinsic_vwadd_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwadd.mask.nxv8i64.nxv8i32.nxv8i32( + , + , + , + , + i32); + +define @intrinsic_vwadd_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.mask.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8( , i8, @@ -990,3 +1170,183 @@ ret %a } + +declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32( + , + i32, + i32); + +define @intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwadd.mask.nxv1i64.nxv1i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwadd_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.mask.nxv1i64.nxv1i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwadd.nxv2i64.nxv2i32.i32( + , + i32, + i32); + +define @intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwadd.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.nxv2i64.nxv2i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwadd.mask.nxv2i64.nxv2i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwadd_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.mask.nxv2i64.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwadd.nxv4i64.nxv4i32.i32( + , + i32, + i32); + +define @intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwadd.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.nxv4i64.nxv4i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwadd.mask.nxv4i64.nxv4i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwadd_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.mask.nxv4i64.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwadd.nxv8i64.nxv8i32.i32( + , + i32, + i32); + +define @intrinsic_vwadd_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwadd.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.nxv8i64.nxv8i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwadd.mask.nxv8i64.nxv8i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwadd_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwadd.mask.nxv8i64.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll @@ -496,6 +496,186 @@ ret %a } +declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32( + , + , + i32); + +define @intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32( + , + , + , + , + i32); + +define @intrinsic_vwaddu_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.nxv2i64.nxv2i32.nxv2i32( + , + , + i32); + +define @intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwaddu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.nxv2i32( + , + , + , + , + i32); + +define @intrinsic_vwaddu_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32( + , + , + i32); + +define @intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwaddu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.nxv4i32( + , + , + , + , + i32); + +define @intrinsic_vwaddu_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.nxv8i64.nxv8i32.nxv8i32( + , + , + i32); + +define @intrinsic_vwaddu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwaddu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.nxv8i32( + , + , + , + , + i32); + +define @intrinsic_vwaddu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8( , i8, @@ -990,3 +1170,183 @@ ret %a } + +declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32( + , + i32, + i32); + +define @intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwaddu_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i32( + , + i32, + i32); + +define @intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwaddu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwaddu_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32( + , + i32, + i32); + +define @intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwaddu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwaddu_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.nxv8i64.nxv8i32.i32( + , + i32, + i32); + +define @intrinsic_vwaddu_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwaddu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.nxv8i64.nxv8i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwaddu_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll @@ -498,6 +498,187 @@ ret %a } +declare @llvm.riscv.vwaddu.w.nxv1i64.nxv1i32( + , + , + i32); + +define @intrinsic_vwaddu.w_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.nxv1i64.nxv1i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.mask.nxv1i64.nxv1i32( + , + , + , + , + i32); + +define @intrinsic_vwaddu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.mask.nxv1i64.nxv1i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.nxv2i64.nxv2i32( + , + , + i32); + +define @intrinsic_vwaddu.w_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwaddu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.nxv2i64.nxv2i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.mask.nxv2i64.nxv2i32( + , + , + , + , + i32); + +define @intrinsic_vwaddu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.mask.nxv2i64.nxv2i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32( + , + , + i32); + +define @intrinsic_vwaddu.w_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwaddu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.mask.nxv4i64.nxv4i32( + , + , + , + , + i32); + +define @intrinsic_vwaddu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.mask.nxv4i64.nxv4i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.nxv8i64.nxv8i32( + , + , + i32); + +define @intrinsic_vwaddu.w_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwaddu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.nxv8i64.nxv8i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32( + , + , + , + , + i32); + +define @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vwaddu.w.nxv1i16.i8( , i8, @@ -992,3 +1173,183 @@ ret %a } + +declare @llvm.riscv.vwaddu.w.nxv1i64.i32( + , + i32, + i32); + +define @intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.nxv1i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.mask.nxv1i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwaddu.w_mask_wx_nxv1i64_nxv1i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.mask.nxv1i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.nxv2i64.i32( + , + i32, + i32); + +define @intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwaddu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.nxv2i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.mask.nxv2i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwaddu.w_mask_wx_nxv2i64_nxv2i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.mask.nxv2i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.nxv4i64.i32( + , + i32, + i32); + +define @intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwaddu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.nxv4i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.mask.nxv4i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwaddu.w_mask_wx_nxv4i64_nxv4i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.mask.nxv4i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.nxv8i64.i32( + , + i32, + i32); + +define @intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwaddu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.nxv8i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwaddu.w.mask.nxv8i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwaddu.w_mask_wx_nxv8i64_nxv8i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwaddu.w.mask.nxv8i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll @@ -496,6 +496,186 @@ ret %a } +declare @llvm.riscv.vwsub.nxv1i64.nxv1i32.nxv1i32( + , + , + i32); + +define @intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.nxv1i64.nxv1i32.nxv1i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsub.mask.nxv1i64.nxv1i32.nxv1i32( + , + , + , + , + i32); + +define @intrinsic_vwsub_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.mask.nxv1i64.nxv1i32.nxv1i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsub.nxv2i64.nxv2i32.nxv2i32( + , + , + i32); + +define @intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsub.mask.nxv2i64.nxv2i32.nxv2i32( + , + , + , + , + i32); + +define @intrinsic_vwsub_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.mask.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsub.nxv4i64.nxv4i32.nxv4i32( + , + , + i32); + +define @intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsub.mask.nxv4i64.nxv4i32.nxv4i32( + , + , + , + , + i32); + +define @intrinsic_vwsub_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.mask.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsub.nxv8i64.nxv8i32.nxv8i32( + , + , + i32); + +define @intrinsic_vwsub_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsub.mask.nxv8i64.nxv8i32.nxv8i32( + , + , + , + , + i32); + +define @intrinsic_vwsub_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.mask.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8( , i8, @@ -990,3 +1170,183 @@ ret %a } + +declare @llvm.riscv.vwsub.nxv1i64.nxv1i32.i32( + , + i32, + i32); + +define @intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.nxv1i64.nxv1i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsub.mask.nxv1i64.nxv1i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsub_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.mask.nxv1i64.nxv1i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsub.nxv2i64.nxv2i32.i32( + , + i32, + i32); + +define @intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwsub.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.nxv2i64.nxv2i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsub.mask.nxv2i64.nxv2i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsub_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.mask.nxv2i64.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsub.nxv4i64.nxv4i32.i32( + , + i32, + i32); + +define @intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwsub.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.nxv4i64.nxv4i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsub.mask.nxv4i64.nxv4i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsub_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.mask.nxv4i64.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsub.nxv8i64.nxv8i32.i32( + , + i32, + i32); + +define @intrinsic_vwsub_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwsub.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.nxv8i64.nxv8i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsub.mask.nxv8i64.nxv8i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsub_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsub.mask.nxv8i64.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll @@ -496,6 +496,186 @@ ret %a } +declare @llvm.riscv.vwsubu.nxv1i64.nxv1i32.nxv1i32( + , + , + i32); + +define @intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.nxv1i64.nxv1i32.nxv1i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.mask.nxv1i64.nxv1i32.nxv1i32( + , + , + , + , + i32); + +define @intrinsic_vwsubu_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.mask.nxv1i64.nxv1i32.nxv1i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.nxv2i64.nxv2i32.nxv2i32( + , + , + i32); + +define @intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwsubu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.mask.nxv2i64.nxv2i32.nxv2i32( + , + , + , + , + i32); + +define @intrinsic_vwsubu_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.mask.nxv2i64.nxv2i32.nxv2i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.nxv4i64.nxv4i32.nxv4i32( + , + , + i32); + +define @intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwsubu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.mask.nxv4i64.nxv4i32.nxv4i32( + , + , + , + , + i32); + +define @intrinsic_vwsubu_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.mask.nxv4i64.nxv4i32.nxv4i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.nxv8i64.nxv8i32.nxv8i32( + , + , + i32); + +define @intrinsic_vwsubu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwsubu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.mask.nxv8i64.nxv8i32.nxv8i32( + , + , + , + , + i32); + +define @intrinsic_vwsubu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.mask.nxv8i64.nxv8i32.nxv8i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8( , i8, @@ -990,3 +1170,183 @@ ret %a } + +declare @llvm.riscv.vwsubu.nxv1i64.nxv1i32.i32( + , + i32, + i32); + +define @intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.nxv1i64.nxv1i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.mask.nxv1i64.nxv1i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsubu_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.mask.nxv1i64.nxv1i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.nxv2i64.nxv2i32.i32( + , + i32, + i32); + +define @intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwsubu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.nxv2i64.nxv2i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.mask.nxv2i64.nxv2i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsubu_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.mask.nxv2i64.nxv2i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.nxv4i64.nxv4i32.i32( + , + i32, + i32); + +define @intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwsubu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.nxv4i64.nxv4i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.mask.nxv4i64.nxv4i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsubu_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.mask.nxv4i64.nxv4i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.nxv8i64.nxv8i32.i32( + , + i32, + i32); + +define @intrinsic_vwsubu_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwsubu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.nxv8i64.nxv8i32.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.mask.nxv8i64.nxv8i32.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsubu_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.mask.nxv8i64.nxv8i32.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll @@ -498,6 +498,187 @@ ret %a } +declare @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32( + , + , + i32); + +define @intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.mask.nxv1i64.nxv1i32( + , + , + , + , + i32); + +define @intrinsic_vwsubu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.mask.nxv1i64.nxv1i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32( + , + , + i32); + +define @intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwsubu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.mask.nxv2i64.nxv2i32( + , + , + , + , + i32); + +define @intrinsic_vwsubu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.mask.nxv2i64.nxv2i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32( + , + , + i32); + +define @intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwsubu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.mask.nxv4i64.nxv4i32( + , + , + , + , + i32); + +define @intrinsic_vwsubu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.mask.nxv4i64.nxv4i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.nxv8i64.nxv8i32( + , + , + i32); + +define @intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwsubu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.nxv8i64.nxv8i32( + %0, + %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32( + , + , + , + , + i32); + +define @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32( + %0, + %1, + %2, + %3, + i32 %4) + + ret %a +} + declare @llvm.riscv.vwsubu.w.nxv1i16.i8( , i8, @@ -992,3 +1173,183 @@ ret %a } + +declare @llvm.riscv.vwsubu.w.nxv1i64.i32( + , + i32, + i32); + +define @intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.nxv1i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.mask.nxv1i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsubu.w_mask_wx_nxv1i64_nxv1i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.mask.nxv1i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.nxv2i64.i32( + , + i32, + i32); + +define @intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwsubu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.nxv2i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.mask.nxv2i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsubu.w_mask_wx_nxv2i64_nxv2i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.mask.nxv2i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.nxv4i64.i32( + , + i32, + i32); + +define @intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwsubu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.nxv4i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.mask.nxv4i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsubu.w_mask_wx_nxv4i64_nxv4i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.mask.nxv4i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.nxv8i64.i32( + , + i32, + i32); + +define @intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwsubu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.nxv8i64.i32( + %0, + i32 %1, + i32 %2) + + ret %a +} + +declare @llvm.riscv.vwsubu.w.mask.nxv8i64.i32( + , + , + i32, + , + i32); + +define @intrinsic_vwsubu.w_mask_wx_nxv8i64_nxv8i64_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) +entry: + %a = call @llvm.riscv.vwsubu.w.mask.nxv8i64.i32( + %0, + %1, + i32 %2, + %3, + i32 %4) + + ret %a +}