diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h --- a/llvm/include/llvm/MC/MCRegisterInfo.h +++ b/llvm/include/llvm/MC/MCRegisterInfo.h @@ -39,6 +39,7 @@ const uint16_t RegsSize; const uint16_t RegSetSize; const uint16_t ID; + const uint16_t RegSizeInBits; const int8_t CopyCost; const bool Allocatable; @@ -78,6 +79,12 @@ return contains(Reg1) && contains(Reg2); } + /// Return the size of the physical register in bits if we are able to + /// determine it. This always returns zero for registers of targets that use + /// HW modes, as we need more information to determine the size of registers + /// in such cases. Use TargetRegisterInfo to cover them. + unsigned getSizeInBits() const { return RegSizeInBits; } + /// getCopyCost - Return the cost of copying a value between two registers in /// this class. A negative number means the register class is very expensive /// to copy e.g. status flag register classes. diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -1084,12 +1084,15 @@ for (const auto &RC : RegisterClasses) { assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); + uint32_t RegSize = 0; + if (RC.RSI.isSimple()) + RegSize = RC.RSI.getSimple().RegSize; OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " - << RegClassStrings.get(RC.getName()) << ", " - << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " - << RC.getQualifiedName() + "RegClassID" << ", " - << RC.CopyCost << ", " - << ( RC.Allocatable ? "true" : "false" ) << " },\n"; + << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() + << ", sizeof(" << RC.getName() << "Bits), " + << RC.getQualifiedName() + "RegClassID" + << ", " << RegSize << ", " << RC.CopyCost << ", " + << (RC.Allocatable ? "true" : "false") << " },\n"; } OS << "};\n\n";