diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h --- a/llvm/include/llvm/MC/MCRegisterInfo.h +++ b/llvm/include/llvm/MC/MCRegisterInfo.h @@ -39,6 +39,7 @@ const uint16_t RegsSize; const uint16_t RegSetSize; const uint16_t ID; + const uint16_t PhysRegSize; const int8_t CopyCost; const bool Allocatable; @@ -78,6 +79,11 @@ return contains(Reg1) && contains(Reg2); } + /// Return the size of the physical register in bytes. + unsigned getPhysRegSize() const { return PhysRegSize; } + /// Temporary function to allow out-of-tree targets to switch. + unsigned getSize() const { return getPhysRegSize(); } + /// getCopyCost - Return the cost of copying a value between two registers in /// this class. A negative number means the register class is very expensive /// to copy e.g. status flag register classes. diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -397,7 +397,8 @@ return true; } unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); - // Convert bit size to byte size. + // Convert bit size to byte size to be consistent with + // MCRegisterClass::getSize(). if (BitSize % 8) return false; diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -1084,10 +1084,14 @@ for (const auto &RC : RegisterClasses) { assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); + uint32_t RegSize = 0; + if (RC.RSI.isSimple()) + RegSize = RC.RSI.getSimple().RegSize; OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " << RC.getQualifiedName() + "RegClassID" << ", " + << RegSize/8 << ", " << RC.CopyCost << ", " << ( RC.Allocatable ? "true" : "false" ) << " },\n"; }