diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -452,7 +452,7 @@
     // For Power9 we allow the user to enable GPR to vector spills.
     // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
     // support to spill GPRC.
-    if (TM.isELFv2ABI()) {
+    if (TM.isELFv2ABI() || Subtarget.isAIXABI()) {
       if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
           RC == &PPC::G8RCRegClass) {
         InflateGP8RC++;
diff --git a/llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll b/llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll
--- a/llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll
@@ -1,4 +1,6 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills  < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -ppc-enable-gpr-to-vsr-spills -vec-extabi < %s | FileCheck %s
+
 define signext i32 @foo(i32 signext %a, i32 signext %b) {
 entry:
   %cmp = icmp slt i32 %a, %b