diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
--- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
@@ -1055,6 +1055,7 @@
   Register SrcLoReg, SrcHiReg;
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
+  bool DstIsUndef = MI.getOperand(0).isUndef();
   bool SrcIsKill = MI.getOperand(1).isKill();
   unsigned OpLo = AVR::STPtrRr;
   unsigned OpHi = AVR::STDPtrQRr;
@@ -1062,11 +1063,11 @@
 
   //:TODO: need to reverse this order like inw and stsw?
   auto MIBLO = buildMI(MBB, MBBI, OpLo)
-    .addReg(DstReg)
+    .addReg(DstReg, getUndefRegState(DstIsUndef))
     .addReg(SrcLoReg, getKillRegState(SrcIsKill));
 
   auto MIBHI = buildMI(MBB, MBBI, OpHi)
-    .addReg(DstReg)
+    .addReg(DstReg, getUndefRegState(DstIsUndef))
     .addImm(1)
     .addReg(SrcHiReg, getKillRegState(SrcIsKill));
 
@@ -1435,7 +1436,7 @@
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, getKillRegState(DstIsKill))
-          .addReg(DstLoReg, getKillRegState(DstIsKill));
+          .addReg(DstLoReg);
   // SREG is implicitly dead.
   MI1->getOperand(3).setIsDead();
 
@@ -1453,7 +1454,7 @@
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstHiReg, getKillRegState(DstIsKill))
-          .addReg(DstLoReg, getKillRegState(DstIsKill));
+          .addReg(DstLoReg);
   if (ImpIsDead)
     MI3->getOperand(3).setIsDead();
 
@@ -1474,7 +1475,7 @@
   // mov Rh, Rl
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg);
 
   // clr Rl
   auto MIBLO =
@@ -1502,7 +1503,7 @@
   // mov Rh, Rl
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg);
 
   // swap Rh
   buildMI(MBB, MBBI, AVR::SWAPRd)
@@ -1595,7 +1596,7 @@
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstLoReg, getKillRegState(DstIsKill))
-          .addReg(DstHiReg, getKillRegState(DstIsKill));
+          .addReg(DstHiReg);
   // SREG is implicitly dead.
   MI1->getOperand(3).setIsDead();
 
@@ -1613,7 +1614,7 @@
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
           .addReg(DstLoReg, getKillRegState(DstIsKill))
-          .addReg(DstHiReg, getKillRegState(DstIsKill));
+          .addReg(DstHiReg);
   if (ImpIsDead)
     MI3->getOperand(3).setIsDead();
 
@@ -1747,7 +1748,7 @@
   // Move upper byte to lower byte.
   buildMI(MBB, MBBI, AVR::MOVRdRr)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg);
 
   // Move the sign bit to the C flag.
   buildMI(MBB, MBBI, AVR::ADDRdRr)
@@ -1782,7 +1783,8 @@
 
   buildMI(MBB, MBBI, AVR::RORRd)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, getKillRegState(DstIsKill))
+      ->getOperand(3).setIsUndef(true);
 
   buildMI(MBB, MBBI, AVR::EORRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -1819,7 +1821,8 @@
   buildMI(MBB, MBBI, AVR::ADCRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
       .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, getKillRegState(DstIsKill))
+      ->getOperand(4).setIsUndef(true);
 
   buildMI(MBB, MBBI, AVR::EORRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -1958,8 +1961,8 @@
 
   auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-    .addReg(DstHiReg, RegState::Kill)
-    .addReg(DstHiReg, RegState::Kill);
+    .addReg(DstHiReg, RegState::Kill | RegState::Undef)
+    .addReg(DstHiReg, RegState::Kill | RegState::Undef);
 
   if (ImpIsDead)
     EOR->getOperand(3).setIsDead();
diff --git a/llvm/lib/Target/AVR/AVRFrameLowering.cpp b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
--- a/llvm/lib/Target/AVR/AVRFrameLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
@@ -362,7 +362,7 @@
       New->getOperand(3).setIsDead();
 
       BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
-          .addReg(AVR::R31R30, RegState::Kill);
+          .addReg(AVR::R31R30);
 
       // Make sure the remaining stack stores are converted to real store
       // instructions.
diff --git a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
@@ -14,6 +14,7 @@
 name:            test_adcwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20, $sreg
 
     ; CHECK-LABEL: test_adcwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
@@ -14,6 +14,7 @@
 name:            test_addwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_addwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
--- a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
@@ -14,6 +14,7 @@
 name:            test_andiwrdrr
 body: |
   bb.0.entry:
+    liveins: $r17r16
 
     ; CHECK-LABEL: test_andiwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
@@ -14,6 +14,7 @@
 name:            test_andwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_andwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir
--- a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir
@@ -12,6 +12,7 @@
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
--- a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
@@ -14,6 +14,7 @@
 name:            test_comwrd
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test_comwrd
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
@@ -14,6 +14,7 @@
 name:            test_cpcwrdrr
 body: |
   bb.0.entry:
+    liveins: $r21r20, $r23r22, $sreg
 
     ; CHECK-LABEL: test_cpcwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
@@ -14,6 +14,7 @@
 name:            test_cpwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_cpwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
@@ -14,6 +14,7 @@
 name:            test_eorwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_eorwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir
--- a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir
@@ -18,6 +18,7 @@
   - { id: 0, class: _ }
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
--- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
@@ -15,6 +15,7 @@
 tracksRegLiveness: true
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_lddwrdptrq
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
--- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
@@ -15,6 +15,7 @@
 tracksRegLiveness: true
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_ldwrdptr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
@@ -14,6 +14,7 @@
 name:            test_ldwrdptr
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_ldwrdptr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
--- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
@@ -14,6 +14,7 @@
 name:            test_ldwrdptrpd
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_ldwrdptrpd
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
--- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
@@ -14,6 +14,7 @@
 name:            test_ldwrdptrpi
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_ldwrdptrpi
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir
--- a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir
@@ -12,6 +12,7 @@
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir
--- a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir
@@ -12,6 +12,7 @@
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir b/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
--- a/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
@@ -14,6 +14,7 @@
 name:            test_negwrd
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test_negwrd
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
--- a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
@@ -14,6 +14,7 @@
 name:            test_oriwrdrr
 body: |
   bb.0.entry:
+    liveins: $r21r20
 
     ; CHECK-LABEL: test_oriwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
@@ -14,6 +14,7 @@
 name:            test_orwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20
 
     ; CHECK-LABEL: test_orwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir
@@ -12,6 +12,7 @@
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r15r14
 
     ; CHECK-LABEL: test
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
--- a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
@@ -14,6 +14,7 @@
 name:            test_sbciwrdk
 body: |
   bb.0.entry:
+    liveins: $r21r20, $sreg
 
     ; CHECK-LABEL: test_sbciwrdk
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
@@ -14,6 +14,7 @@
 name:            test_sbcwrdrr
 body: |
   bb.0.entry:
+    liveins: $r15r14, $r21r20, $sreg
 
     ; CHECK-LABEL: test_sbcwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir
--- a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir
@@ -12,6 +12,7 @@
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r31
 
     ; CHECK-LABEL: test
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir
@@ -14,6 +14,7 @@
 name:            test_stswkrr
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test_stswkrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
@@ -12,6 +12,7 @@
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
@@ -12,6 +12,7 @@
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r31r30
 
     ; CHECK-LABEL: test
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir
@@ -14,6 +14,7 @@
 name:            test_stwptrrr
 body: |
   bb.0.entry:
+    liveins: $r31r30, $r17r16
 
     ; CHECK-LABEL: test_stwptrrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
--- a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
@@ -14,6 +14,7 @@
 name:            test_subiwrdrr
 body: |
   bb.0.entry:
+    liveins: $r21r20
 
     ; CHECK-LABEL: test_subiwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
--- a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
@@ -14,6 +14,7 @@
 name:            test_subwrdrr
 body: |
   bb.0.entry:
+    liveins: $r21r20, $r15r14
 
     ; CHECK-LABEL: test_subwrdrr
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
--- a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
@@ -12,6 +12,7 @@
 name:            test
 body: |
   bb.0.entry:
+    liveins: $r31
 
     ; CHECK-LABEL: test