diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -545,13 +545,18 @@
       // or do an unmerge to get the lower block of elements.
       if (VATy.isVector() &&
           VATy.getNumElements() > OrigVT.getVectorNumElements()) {
-        // Just handle the case where the VA type is 2 * original type.
-        if (VATy.getNumElements() != OrigVT.getVectorNumElements() * 2) {
-          LLVM_DEBUG(dbgs()
-                     << "Incoming promoted vector arg has too many elts");
+        // Just handle the case where the VA type is a multiple original type.
+        if (VATy.getNumElements() % OrigVT.getVectorNumElements() != 0) {
+          LLVM_DEBUG(dbgs() << "Incoming promoted vector arg elts is not a "
+                               "multiple of orig type elt");
           return false;
         }
-        auto Unmerge = MIRBuilder.buildUnmerge({OrigTy, OrigTy}, {NewReg});
+        SmallVector<LLT, 4> DstTys;
+        unsigned NumParts =
+            VATy.getNumElements() / OrigVT.getVectorNumElements();
+        for (unsigned Idx = 0; Idx < NumParts; ++Idx)
+          DstTys.push_back(OrigTy);
+        auto Unmerge = MIRBuilder.buildUnmerge(DstTys, {NewReg});
         MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0));
       } else {
         MIRBuilder.buildTrunc(ArgReg, {NewReg}).getReg(0);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+define i8 @v1s8_add(<1 x i8> %a0) nounwind {
+  ; CHECK-LABEL: name: v1s8_add
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $d0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+  ; CHECK:   [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s8) = COPY [[UV]](s8)
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY1]](s8)
+  ; CHECK:   $w0 = COPY [[ANYEXT]](s32)
+  ; CHECK:   RET_ReallyLR implicit $w0
+  %res = bitcast <1 x i8> %a0 to i8
+  ret i8 %res
+}