diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
@@ -33,66 +33,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, i64)
 declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
@@ -124,7547 +64,8017 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv1i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i64:
+define void @test_vsuxseg2_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
 ; CHECK-NEXT:    vmv4r.v v12, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i64:
+define void @test_vsuxseg2_mask_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
 ; CHECK-NEXT:    vmv4r.v v12, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i32:
+define void @test_vsuxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i32:
+define void @test_vsuxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i16:
+define void @test_vsuxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i16:
+define void @test_vsuxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i8:
+define void @test_vsuxseg2_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i8:
+define void @test_vsuxseg2_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i16:
+define void @test_vsuxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i16:
+define void @test_vsuxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i32:
+define void @test_vsuxseg3_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i32:
+define void @test_vsuxseg3_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i8:
+define void @test_vsuxseg3_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i8:
+define void @test_vsuxseg3_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv4i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i64:
+define void @test_vsuxseg3_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i64:
+define void @test_vsuxseg3_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv64i8:
+define void @test_vsuxseg3_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv64i8:
+define void @test_vsuxseg3_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i16:
+define void @test_vsuxseg4_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i16:
+define void @test_vsuxseg4_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv8i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i64:
+define void @test_vsuxseg4_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i64:
+define void @test_vsuxseg4_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i8:
+define void @test_vsuxseg4_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i8:
+define void @test_vsuxseg4_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i8:
+define void @test_vsuxseg4_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i8:
+define void @test_vsuxseg4_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i32:
+define void @test_vsuxseg2_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i32:
+define void @test_vsuxseg2_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv32i8:
+define void @test_vsuxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv32i8:
+define void @test_vsuxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i32:
+define void @test_vsuxseg2_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i32:
+define void @test_vsuxseg2_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i16:
+define void @test_vsuxseg3_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i16:
+define void @test_vsuxseg3_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i16_nxv2i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i64:
+define void @test_vsuxseg3_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i64:
+define void @test_vsuxseg3_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i16:
+define void @test_vsuxseg3_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i16:
+define void @test_vsuxseg3_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv32i16:
+define void @test_vsuxseg4_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv32i16:
+define void @test_vsuxseg4_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i32:
+define void @test_vsuxseg4_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i32:
+define void @test_vsuxseg4_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i8:
+define void @test_vsuxseg4_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i8:
+define void @test_vsuxseg4_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i64:
+define void @test_vsuxseg2_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i64:
+define void @test_vsuxseg2_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i32:
+define void @test_vsuxseg2_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i32:
+define void @test_vsuxseg2_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i16:
+define void @test_vsuxseg2_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i16:
+define void @test_vsuxseg2_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i8:
+define void @test_vsuxseg2_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i8:
+define void @test_vsuxseg2_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i16:
+define void @test_vsuxseg3_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i16:
+define void @test_vsuxseg3_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i32:
+define void @test_vsuxseg3_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i32:
+define void @test_vsuxseg3_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i8:
+define void @test_vsuxseg3_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i8:
+define void @test_vsuxseg3_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i64:
+define void @test_vsuxseg3_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i64:
+define void @test_vsuxseg3_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv64i8:
+define void @test_vsuxseg4_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv64i8:
+define void @test_vsuxseg4_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i16:
+define void @test_vsuxseg4_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i16:
+define void @test_vsuxseg4_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i64:
+define void @test_vsuxseg4_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i64:
+define void @test_vsuxseg4_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i8:
+define void @test_vsuxseg4_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i8:
+define void @test_vsuxseg4_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i8:
+define void @test_vsuxseg5_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i8:
+define void @test_vsuxseg5_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv32i8:
+define void @test_vsuxseg5_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv32i8:
+define void @test_vsuxseg5_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i32:
+define void @test_vsuxseg5_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i32:
+define void @test_vsuxseg5_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i16:
+define void @test_vsuxseg5_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i16:
+define void @test_vsuxseg5_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i64:
+define void @test_vsuxseg6_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i64:
+define void @test_vsuxseg6_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i16:
+define void @test_vsuxseg6_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i16:
+define void @test_vsuxseg6_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv32i16:
+define void @test_vsuxseg6_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv32i16:
+define void @test_vsuxseg6_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i32:
+define void @test_vsuxseg6_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i32:
+define void @test_vsuxseg6_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i8:
+define void @test_vsuxseg7_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i8:
+define void @test_vsuxseg7_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i64:
+define void @test_vsuxseg7_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i64:
+define void @test_vsuxseg7_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i32:
+define void @test_vsuxseg7_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i32:
+define void @test_vsuxseg7_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i16:
+define void @test_vsuxseg7_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i16:
+define void @test_vsuxseg7_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i8:
+define void @test_vsuxseg8_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i8:
+define void @test_vsuxseg8_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i16:
+define void @test_vsuxseg8_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i16:
+define void @test_vsuxseg8_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i32:
+define void @test_vsuxseg8_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i32:
+define void @test_vsuxseg8_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i8:
+define void @test_vsuxseg8_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i8:
+define void @test_vsuxseg8_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i64:
+define void @test_vsuxseg2_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i64:
+define void @test_vsuxseg2_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv64i8:
+define void @test_vsuxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv64i8:
+define void @test_vsuxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i16:
+define void @test_vsuxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i16:
+define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i64:
+define void @test_vsuxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i64:
+define void @test_vsuxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i8:
+define void @test_vsuxseg3_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i8:
+define void @test_vsuxseg3_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i8:
+define void @test_vsuxseg3_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i8:
+define void @test_vsuxseg3_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i32:
+define void @test_vsuxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i32:
+define void @test_vsuxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv32i8:
+define void @test_vsuxseg3_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv32i8:
+define void @test_vsuxseg3_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i32:
+define void @test_vsuxseg4_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i32:
+define void @test_vsuxseg4_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i16:
+define void @test_vsuxseg4_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i16:
+define void @test_vsuxseg4_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i64:
+define void @test_vsuxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i64:
+define void @test_vsuxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i16:
+define void @test_vsuxseg4_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i16:
+define void @test_vsuxseg4_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv32i16:
+define void @test_vsuxseg5_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv32i16:
+define void @test_vsuxseg5_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i32:
+define void @test_vsuxseg5_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i32:
+define void @test_vsuxseg5_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i8:
+define void @test_vsuxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i8:
+define void @test_vsuxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i64:
+define void @test_vsuxseg5_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i64:
+define void @test_vsuxseg5_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i32:
+define void @test_vsuxseg6_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i32:
+define void @test_vsuxseg6_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i16:
+define void @test_vsuxseg6_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i16:
+define void @test_vsuxseg6_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i8:
+define void @test_vsuxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i8:
+define void @test_vsuxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i16:
+define void @test_vsuxseg6_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i16:
+define void @test_vsuxseg6_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i32:
+define void @test_vsuxseg7_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i32:
+define void @test_vsuxseg7_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i8:
+define void @test_vsuxseg7_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i8:
+define void @test_vsuxseg7_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i64:
+define void @test_vsuxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i64:
+define void @test_vsuxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv64i8:
+define void @test_vsuxseg7_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv64i8:
+define void @test_vsuxseg7_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i16:
+define void @test_vsuxseg8_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i16:
+define void @test_vsuxseg8_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i64:
+define void @test_vsuxseg8_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i64:
+define void @test_vsuxseg8_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i8:
+define void @test_vsuxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i8:
+define void @test_vsuxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i8:
+define void @test_vsuxseg8_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i8:
+define void @test_vsuxseg8_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i32:
+define void @test_vsuxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i32:
+define void @test_vsuxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv32i8:
+define void @test_vsuxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv32i8:
+define void @test_vsuxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i32:
+define void @test_vsuxseg2_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i32:
+define void @test_vsuxseg2_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsuxseg2_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsuxseg2_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i16:
+define void @test_vsuxseg3_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i16:
+define void @test_vsuxseg3_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i64:
+define void @test_vsuxseg3_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i64:
+define void @test_vsuxseg3_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i16:
+define void @test_vsuxseg3_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i16:
+define void @test_vsuxseg3_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv32i16:
+define void @test_vsuxseg3_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv32i16:
+define void @test_vsuxseg3_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i32:
+define void @test_vsuxseg4_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i32:
+define void @test_vsuxseg4_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i8:
+define void @test_vsuxseg4_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i8:
+define void @test_vsuxseg4_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i64:
+define void @test_vsuxseg4_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i64:
+define void @test_vsuxseg4_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i32:
+define void @test_vsuxseg4_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i32:
+define void @test_vsuxseg4_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i16:
+define void @test_vsuxseg2_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i16:
+define void @test_vsuxseg2_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i8:
+define void @test_vsuxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i8:
+define void @test_vsuxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i16:
+define void @test_vsuxseg2_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i16:
+define void @test_vsuxseg2_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i32:
+define void @test_vsuxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i32:
+define void @test_vsuxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i8:
+define void @test_vsuxseg3_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i8:
+define void @test_vsuxseg3_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i64:
+define void @test_vsuxseg3_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i64:
+define void @test_vsuxseg3_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv64i8:
+define void @test_vsuxseg3_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv64i8:
+define void @test_vsuxseg3_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i16:
+define void @test_vsuxseg3_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i16:
+define void @test_vsuxseg3_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i64:
+define void @test_vsuxseg4_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i64:
+define void @test_vsuxseg4_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i8:
+define void @test_vsuxseg4_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i8:
+define void @test_vsuxseg4_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i8:
+define void @test_vsuxseg4_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i8:
+define void @test_vsuxseg4_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i32:
+define void @test_vsuxseg4_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i32:
+define void @test_vsuxseg4_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv32i8:
+define void @test_vsuxseg5_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv32i8:
+define void @test_vsuxseg5_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i32:
+define void @test_vsuxseg5_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i32:
+define void @test_vsuxseg5_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i16:
+define void @test_vsuxseg5_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i16:
+define void @test_vsuxseg5_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i64:
+define void @test_vsuxseg5_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i64:
+define void @test_vsuxseg5_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i16:
+define void @test_vsuxseg6_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i16:
+define void @test_vsuxseg6_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv32i16:
+define void @test_vsuxseg6_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv32i16:
+define void @test_vsuxseg6_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i32:
+define void @test_vsuxseg6_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i32:
+define void @test_vsuxseg6_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i8:
+define void @test_vsuxseg6_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i8:
+define void @test_vsuxseg6_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i64:
+define void @test_vsuxseg7_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i64:
+define void @test_vsuxseg7_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i32:
+define void @test_vsuxseg7_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i32:
+define void @test_vsuxseg7_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i16:
+define void @test_vsuxseg7_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i16:
+define void @test_vsuxseg7_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i8:
+define void @test_vsuxseg7_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i8:
+define void @test_vsuxseg7_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i16:
+define void @test_vsuxseg8_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i16:
+define void @test_vsuxseg8_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i32:
+define void @test_vsuxseg8_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i32:
+define void @test_vsuxseg8_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i8:
+define void @test_vsuxseg8_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i8:
+define void @test_vsuxseg8_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i64:
+define void @test_vsuxseg8_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i64:
+define void @test_vsuxseg8_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv64i8:
+define void @test_vsuxseg2_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv64i8:
+define void @test_vsuxseg2_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i16:
+define void @test_vsuxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i16:
+define void @test_vsuxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i64:
+define void @test_vsuxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i64:
+define void @test_vsuxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i8:
+define void @test_vsuxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i8:
+define void @test_vsuxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i8:
+define void @test_vsuxseg3_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i8:
+define void @test_vsuxseg3_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i32:
+define void @test_vsuxseg3_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i32:
+define void @test_vsuxseg3_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv32i8:
+define void @test_vsuxseg3_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv32i8:
+define void @test_vsuxseg3_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i32:
+define void @test_vsuxseg3_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i32:
+define void @test_vsuxseg3_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i16:
+define void @test_vsuxseg4_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i16:
+define void @test_vsuxseg4_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg3_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i64:
+define void @test_vsuxseg4_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i64:
+define void @test_vsuxseg4_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i16:
+define void @test_vsuxseg4_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i16:
+define void @test_vsuxseg4_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv32i16:
+define void @test_vsuxseg4_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv32i16:
+define void @test_vsuxseg4_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i32:
+define void @test_vsuxseg5_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i32:
+define void @test_vsuxseg5_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i8:
+define void @test_vsuxseg5_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i8:
+define void @test_vsuxseg5_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i64:
+define void @test_vsuxseg5_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i64:
+define void @test_vsuxseg5_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i32:
+define void @test_vsuxseg5_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i32:
+define void @test_vsuxseg5_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i16:
+define void @test_vsuxseg6_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i16:
+define void @test_vsuxseg6_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i8:
+define void @test_vsuxseg6_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i8:
+define void @test_vsuxseg6_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i16:
+define void @test_vsuxseg6_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i16:
+define void @test_vsuxseg6_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i32:
+define void @test_vsuxseg6_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i32:
+define void @test_vsuxseg6_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i8:
+define void @test_vsuxseg7_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i8:
+define void @test_vsuxseg7_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i64:
+define void @test_vsuxseg7_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i64:
+define void @test_vsuxseg7_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv64i8:
+define void @test_vsuxseg7_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv64i8:
+define void @test_vsuxseg7_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i16:
+define void @test_vsuxseg7_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i16:
+define void @test_vsuxseg7_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i64:
+define void @test_vsuxseg8_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i64:
+define void @test_vsuxseg8_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i8:
+define void @test_vsuxseg8_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i8:
+define void @test_vsuxseg8_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i8:
+define void @test_vsuxseg8_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i8:
+define void @test_vsuxseg8_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i32:
+define void @test_vsuxseg8_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i32:
+define void @test_vsuxseg8_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv32i8:
+define void @test_vsuxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv32i8:
+define void @test_vsuxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i32:
+define void @test_vsuxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i32:
+define void @test_vsuxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i16:
+define void @test_vsuxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i16:
+define void @test_vsuxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i64:
+define void @test_vsuxseg2_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i64:
+define void @test_vsuxseg2_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv16i16:
+define void @test_vsuxseg3_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv16i16:
+define void @test_vsuxseg3_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv32i16:
+define void @test_vsuxseg3_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv32i16:
+define void @test_vsuxseg3_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv4i32:
+define void @test_vsuxseg3_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv4i32:
+define void @test_vsuxseg3_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv16i8:
+define void @test_vsuxseg3_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv16i8:
+define void @test_vsuxseg3_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i64:
+define void @test_vsuxseg4_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i64:
+define void @test_vsuxseg4_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i32:
+define void @test_vsuxseg4_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i32:
+define void @test_vsuxseg4_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv8i16:
+define void @test_vsuxseg4_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv8i16:
+define void @test_vsuxseg4_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv4i8:
+define void @test_vsuxseg4_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv4i8:
+define void @test_vsuxseg4_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i16:
+define void @test_vsuxseg5_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i16:
+define void @test_vsuxseg5_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv2i32:
+define void @test_vsuxseg5_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv2i32:
+define void @test_vsuxseg5_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv8i8:
+define void @test_vsuxseg5_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv8i8:
+define void @test_vsuxseg5_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv4i64:
+define void @test_vsuxseg5_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv4i64:
+define void @test_vsuxseg5_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv64i8:
+define void @test_vsuxseg6_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv64i8:
+define void @test_vsuxseg6_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv4i16:
+define void @test_vsuxseg6_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv4i16:
+define void @test_vsuxseg6_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv8i64:
+define void @test_vsuxseg6_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv8i64:
+define void @test_vsuxseg6_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i8:
+define void @test_vsuxseg6_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i8:
+define void @test_vsuxseg6_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv2i8:
+define void @test_vsuxseg7_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv2i8:
+define void @test_vsuxseg7_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv8i32:
+define void @test_vsuxseg7_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv8i32:
+define void @test_vsuxseg7_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv32i8:
+define void @test_vsuxseg7_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv32i8:
+define void @test_vsuxseg7_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv16i32:
+define void @test_vsuxseg7_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv16i32:
+define void @test_vsuxseg7_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv2i16:
+define void @test_vsuxseg8_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv2i16:
+define void @test_vsuxseg8_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv2i64:
+define void @test_vsuxseg8_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv2i64:
+define void @test_vsuxseg8_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv16i16:
+define void @test_vsuxseg8_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv16i8:
+define void @test_vsuxseg8_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv1i64:
+define void @test_vsuxseg8_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv1i64:
+define void @test_vsuxseg8_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv1i32:
+define void @test_vsuxseg2_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv1i32:
+define void @test_vsuxseg2_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv8i16:
+define void @test_vsuxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv8i16:
+define void @test_vsuxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv4i8:
+define void @test_vsuxseg2_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv4i8:
+define void @test_vsuxseg2_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv1i16:
+define void @test_vsuxseg2_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv1i16:
+define void @test_vsuxseg2_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv2i32:
+define void @test_vsuxseg3_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv2i32:
+define void @test_vsuxseg3_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv8i8:
+define void @test_vsuxseg3_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv8i8:
+define void @test_vsuxseg3_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv64i8:
+define void @test_vsuxseg3_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv64i8:
+define void @test_vsuxseg3_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv8i64:
+define void @test_vsuxseg3_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv8i64:
+define void @test_vsuxseg3_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv1i8:
+define void @test_vsuxseg4_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv1i8:
+define void @test_vsuxseg4_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv2i8:
+define void @test_vsuxseg4_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv2i8:
+define void @test_vsuxseg4_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv32i8:
+define void @test_vsuxseg4_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv32i8:
+define void @test_vsuxseg4_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv16i32:
+define void @test_vsuxseg4_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv16i32:
+define void @test_vsuxseg4_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv2i16:
+define void @test_vsuxseg5_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv2i16:
+define void @test_vsuxseg5_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i64_nxv2i64:
+define void @test_vsuxseg5_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_nxv2i64:
+define void @test_vsuxseg5_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv16i16:
+define void @test_vsuxseg5_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
 ; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv16i16:
+define void @test_vsuxseg5_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
 ; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv32i16:
+define void @test_vsuxseg5_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv32i16:
+define void @test_vsuxseg5_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv4i32:
+define void @test_vsuxseg6_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv4i32:
+define void @test_vsuxseg6_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv16i8:
+define void @test_vsuxseg6_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv16i8:
+define void @test_vsuxseg6_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv1i64:
+define void @test_vsuxseg6_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vmv1r.v v12, v8
+; CHECK-NEXT:    vmv1r.v v13, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv1i64:
+define void @test_vsuxseg6_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vmv1r.v v12, v8
+; CHECK-NEXT:    vmv1r.v v13, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv1i32:
+define void @test_vsuxseg6_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv1i32:
+define void @test_vsuxseg6_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv8i16:
+define void @test_vsuxseg7_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv8i16:
+define void @test_vsuxseg7_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv4i8:
+define void @test_vsuxseg7_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv4i8:
+define void @test_vsuxseg7_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv1i16:
+define void @test_vsuxseg7_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vmv1r.v v12, v8
+; CHECK-NEXT:    vmv1r.v v13, v8
+; CHECK-NEXT:    vmv1r.v v14, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv1i16:
+define void @test_vsuxseg7_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vmv1r.v v12, v8
+; CHECK-NEXT:    vmv1r.v v13, v8
+; CHECK-NEXT:    vmv1r.v v14, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv2i32:
+define void @test_vsuxseg7_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv2i32:
+define void @test_vsuxseg7_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv8i8:
+define void @test_vsuxseg8_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv8i8:
+define void @test_vsuxseg8_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv4i64:
+define void @test_vsuxseg8_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv4i64:
+define void @test_vsuxseg8_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv64i8:
+define void @test_vsuxseg8_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
 ; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v12, v8
+; CHECK-NEXT:    vmv1r.v v13, v8
+; CHECK-NEXT:    vmv1r.v v14, v8
+; CHECK-NEXT:    vmv1r.v v15, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv64i8:
+define void @test_vsuxseg8_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
 ; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v12, v8
+; CHECK-NEXT:    vmv1r.v v13, v8
+; CHECK-NEXT:    vmv1r.v v14, v8
+; CHECK-NEXT:    vmv1r.v v15, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv4i16:
+define void @test_vsuxseg8_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv4i16:
+define void @test_vsuxseg8_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv8i64:
+define void @test_vsuxseg2_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv8i64:
+define void @test_vsuxseg2_mask_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv1i8:
+define void @test_vsuxseg2_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv1i8:
+define void @test_vsuxseg2_mask_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv2i8:
+define void @test_vsuxseg2_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv2i8:
+define void @test_vsuxseg2_mask_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv8i32:
+define void @test_vsuxseg2_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv8i32:
+define void @test_vsuxseg2_mask_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv32i8:
+define void @test_vsuxseg2_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv32i8:
+define void @test_vsuxseg2_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv16i32:
+define void @test_vsuxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv16i32:
+define void @test_vsuxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv2i16:
+define void @test_vsuxseg2_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsuxseg2_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv2i16:
+declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsuxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsuxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i64_nxv2i64:
+define void @test_vsuxseg3_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_nxv2i64:
+define void @test_vsuxseg3_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv16i16:
+define void @test_vsuxseg3_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv16i16:
+define void @test_vsuxseg3_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv32i16:
+define void @test_vsuxseg3_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv32i16:
+define void @test_vsuxseg3_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv4i32:
+define void @test_vsuxseg3_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv4i32:
+define void @test_vsuxseg3_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv16i8:
+define void @test_vsuxseg4_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv16i8:
+define void @test_vsuxseg4_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv1i64:
+define void @test_vsuxseg4_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv1i64:
+define void @test_vsuxseg4_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv1i32:
+define void @test_vsuxseg4_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv1i32:
+define void @test_vsuxseg4_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv8i16:
+define void @test_vsuxseg4_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv8i16:
+define void @test_vsuxseg4_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv4i8:
+define void @test_vsuxseg5_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv4i8:
+define void @test_vsuxseg5_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv1i16:
+define void @test_vsuxseg5_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv1i16:
+define void @test_vsuxseg5_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv2i32:
+define void @test_vsuxseg5_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv2i32:
+define void @test_vsuxseg5_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv8i8:
+define void @test_vsuxseg5_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv8i8:
+define void @test_vsuxseg5_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv4i64:
+define void @test_vsuxseg6_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv4i64:
+define void @test_vsuxseg6_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv4i16:
+define void @test_vsuxseg6_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv4i16:
+define void @test_vsuxseg6_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv8i64:
+define void @test_vsuxseg6_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv8i64:
+define void @test_vsuxseg6_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv1i8:
+define void @test_vsuxseg6_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv1i8:
+define void @test_vsuxseg6_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv2i8:
+define void @test_vsuxseg7_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv2i8:
+define void @test_vsuxseg7_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv8i32:
+define void @test_vsuxseg7_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv8i32:
+define void @test_vsuxseg7_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv32i8:
+define void @test_vsuxseg7_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv32i8:
+define void @test_vsuxseg7_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv16i32:
+define void @test_vsuxseg7_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv16i32:
+define void @test_vsuxseg7_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv2i16:
+define void @test_vsuxseg8_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv2i16:
+define void @test_vsuxseg8_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i64_nxv2i64:
+define void @test_vsuxseg8_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_nxv2i64:
+define void @test_vsuxseg8_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv16i16:
+define void @test_vsuxseg8_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -7672,16 +8082,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv16i16:
+define void @test_vsuxseg8_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -7689,611 +8101,582 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv32i16:
+define void @test_vsuxseg8_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsuxseg8_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg2_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv32i16:
+define void @test_vsuxseg2_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv4i32:
+define void @test_vsuxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv4i32:
+define void @test_vsuxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv16i8:
+define void @test_vsuxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv16i8:
+define void @test_vsuxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv1i64:
+define void @test_vsuxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsuxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsuxseg3_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv1i64:
+define void @test_vsuxseg3_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv1i32:
+define void @test_vsuxseg3_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv1i32:
+define void @test_vsuxseg3_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv8i16:
+define void @test_vsuxseg3_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv8i16:
+define void @test_vsuxseg3_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv4i8:
+define void @test_vsuxseg3_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv4i8:
+define void @test_vsuxseg3_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv1i16:
+define void @test_vsuxseg4_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv1i16:
+define void @test_vsuxseg4_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv2i32:
+define void @test_vsuxseg4_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv2i32:
+define void @test_vsuxseg4_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv8i8:
+define void @test_vsuxseg4_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv8i8:
+define void @test_vsuxseg4_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv4i64:
+define void @test_vsuxseg4_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv4i64:
+define void @test_vsuxseg4_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv64i8:
+define void @test_vsuxseg5_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv64i8:
+define void @test_vsuxseg5_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv4i16:
+define void @test_vsuxseg5_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv4i16:
+define void @test_vsuxseg5_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv1i8:
+define void @test_vsuxseg5_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv1i8:
+define void @test_vsuxseg5_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv2i8:
+define void @test_vsuxseg5_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv2i8:
+define void @test_vsuxseg5_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv8i32:
+define void @test_vsuxseg6_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8301,16 +8684,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv8i32:
+define void @test_vsuxseg6_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8318,19 +8701,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv32i8:
+define void @test_vsuxseg6_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8338,16 +8721,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv32i8:
+define void @test_vsuxseg6_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8355,56 +8738,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv2i16:
+define void @test_vsuxseg6_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8412,16 +8758,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv2i16:
+define void @test_vsuxseg6_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8429,19 +8775,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i64_nxv2i64:
+define void @test_vsuxseg6_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8449,16 +8795,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_nxv2i64:
+define void @test_vsuxseg6_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8466,19 +8812,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv16i16:
+define void @test_vsuxseg7_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8487,16 +8833,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv16i16:
+define void @test_vsuxseg7_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8505,58 +8851,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv4i32:
+define void @test_vsuxseg7_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8565,16 +8872,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv4i32:
+define void @test_vsuxseg7_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8583,19 +8890,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv16i8:
+define void @test_vsuxseg7_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8604,16 +8911,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv16i8:
+define void @test_vsuxseg7_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8622,19 +8929,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv1i64:
+define void @test_vsuxseg7_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8643,16 +8950,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv1i64:
+define void @test_vsuxseg7_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8661,19 +8968,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv1i32:
+define void @test_vsuxseg8_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8682,16 +8989,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv1i32:
+define void @test_vsuxseg8_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8700,19 +9008,20 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv8i16:
+define void @test_vsuxseg8_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8721,16 +9030,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv8i16:
+define void @test_vsuxseg8_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8739,19 +9049,20 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv4i8:
+define void @test_vsuxseg8_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8760,16 +9071,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv4i8:
+define void @test_vsuxseg8_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8778,19 +9090,20 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv1i16:
+define void @test_vsuxseg8_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -8799,16 +9112,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv1i16:
+define void @test_vsuxseg8_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -8817,608 +9131,575 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv2i32:
+define void @test_vsuxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv2i32:
+define void @test_vsuxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv8i8:
+define void @test_vsuxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv8i8:
+define void @test_vsuxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv4i64:
+define void @test_vsuxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv4i64:
+define void @test_vsuxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv64i8:
+define void @test_vsuxseg2_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv64i8:
+define void @test_vsuxseg2_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv4i16:
+define void @test_vsuxseg3_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv4i16:
+define void @test_vsuxseg3_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv8i64:
+define void @test_vsuxseg3_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv8i64:
+define void @test_vsuxseg3_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv1i8:
+define void @test_vsuxseg3_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsuxseg3_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsuxseg3_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsuxseg3_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsuxseg4_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv1i8:
+define void @test_vsuxseg4_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv2i8:
+define void @test_vsuxseg4_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv2i8:
+define void @test_vsuxseg4_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv8i32:
+define void @test_vsuxseg4_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv8i32:
+define void @test_vsuxseg4_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv32i8:
+define void @test_vsuxseg4_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv32i8:
+define void @test_vsuxseg4_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv16i32:
+define void @test_vsuxseg5_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv16i32:
+define void @test_vsuxseg5_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv2i16:
+define void @test_vsuxseg5_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv2i16:
+define void @test_vsuxseg5_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i64_nxv2i64:
+define void @test_vsuxseg5_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_nxv2i64:
+define void @test_vsuxseg5_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv16i16:
+define void @test_vsuxseg5_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv16i16:
+define void @test_vsuxseg5_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv32i16:
+define void @test_vsuxseg6_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv32i16:
+define void @test_vsuxseg6_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv4i32:
+define void @test_vsuxseg6_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9426,18 +9707,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv4i32:
+define void @test_vsuxseg6_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9445,21 +9724,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv16i8:
+define void @test_vsuxseg6_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9467,18 +9744,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv16i8:
+define void @test_vsuxseg6_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9486,21 +9761,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv1i64:
+define void @test_vsuxseg6_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9508,18 +9781,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv1i64:
+define void @test_vsuxseg6_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9527,21 +9798,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv1i32:
+define void @test_vsuxseg7_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9550,17 +9819,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv1i32:
+define void @test_vsuxseg7_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9569,20 +9837,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv8i16:
+define void @test_vsuxseg7_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9591,17 +9858,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv8i16:
+define void @test_vsuxseg7_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9610,20 +9876,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv4i8:
+define void @test_vsuxseg7_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9632,17 +9897,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv4i8:
+define void @test_vsuxseg7_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9651,20 +9915,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv1i16:
+define void @test_vsuxseg7_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9673,17 +9936,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv1i16:
+define void @test_vsuxseg7_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9692,20 +9954,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv2i32:
+define void @test_vsuxseg8_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9715,16 +9976,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv2i32:
+define void @test_vsuxseg8_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9734,19 +9995,19 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv8i8:
+define void @test_vsuxseg8_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9756,16 +10017,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv8i8:
+define void @test_vsuxseg8_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9775,19 +10036,19 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv4i64:
+define void @test_vsuxseg8_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9797,16 +10058,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv4i64:
+define void @test_vsuxseg8_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9816,60 +10077,19 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv4i16:
+define void @test_vsuxseg8_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -9879,16 +10099,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv4i16:
+define void @test_vsuxseg8_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -9898,3405 +10118,3288 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv8i64:
+define void @test_vsuxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv8i64:
+define void @test_vsuxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv1i8:
+define void @test_vsuxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv1i8:
+define void @test_vsuxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv2i8:
+define void @test_vsuxseg2_nxv8i32_nxv8i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv2i8:
+define void @test_vsuxseg2_mask_nxv8i32_nxv8i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv8i32:
+define void @test_vsuxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv8i32:
+define void @test_vsuxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, <vscale x 32 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv32i8:
+define void @test_vsuxseg2_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv32i8:
+define void @test_vsuxseg2_mask_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, <vscale x 32 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv16i32:
+define void @test_vsuxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv16i32:
+define void @test_vsuxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv2i16:
+define void @test_vsuxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv2i16:
+define void @test_vsuxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i64_nxv2i64:
+define void @test_vsuxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_nxv2i64:
+define void @test_vsuxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i16:
+define void @test_vsuxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i16:
+define void @test_vsuxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv32i16:
+define void @test_vsuxseg2_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv32i16:
+define void @test_vsuxseg2_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i32:
+define void @test_vsuxseg3_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i32:
+define void @test_vsuxseg3_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i8:
+define void @test_vsuxseg3_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i8:
+define void @test_vsuxseg3_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i64:
+define void @test_vsuxseg3_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i64:
+define void @test_vsuxseg3_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i32:
+define void @test_vsuxseg3_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i32:
+define void @test_vsuxseg3_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i16:
+define void @test_vsuxseg4_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i16:
+define void @test_vsuxseg4_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i8:
+define void @test_vsuxseg4_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i8:
+define void @test_vsuxseg4_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i16:
+define void @test_vsuxseg4_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i16:
+define void @test_vsuxseg4_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i32:
+define void @test_vsuxseg4_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i32:
+define void @test_vsuxseg4_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i8:
+define void @test_vsuxseg5_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i8:
+define void @test_vsuxseg5_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i64:
+define void @test_vsuxseg5_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i64:
+define void @test_vsuxseg5_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv64i8:
+define void @test_vsuxseg5_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv64i8:
+define void @test_vsuxseg5_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i16:
+define void @test_vsuxseg5_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i16:
+define void @test_vsuxseg5_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i64:
+define void @test_vsuxseg6_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i64:
+define void @test_vsuxseg6_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i8:
+define void @test_vsuxseg6_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i8:
+define void @test_vsuxseg6_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i8:
+define void @test_vsuxseg6_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i8:
+define void @test_vsuxseg6_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i32:
+define void @test_vsuxseg6_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i32:
+define void @test_vsuxseg6_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv32i8:
+define void @test_vsuxseg7_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv32i8:
+define void @test_vsuxseg7_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i32:
+define void @test_vsuxseg7_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i32:
+define void @test_vsuxseg7_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i16:
+define void @test_vsuxseg7_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i16:
+define void @test_vsuxseg7_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg2_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i64:
+define void @test_vsuxseg7_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i64:
+define void @test_vsuxseg7_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i32:
+define void @test_vsuxseg8_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i32:
+define void @test_vsuxseg8_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i8:
+define void @test_vsuxseg8_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i8:
+define void @test_vsuxseg8_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i64:
+define void @test_vsuxseg8_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i64:
+define void @test_vsuxseg8_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i32:
+define void @test_vsuxseg8_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i32:
+define void @test_vsuxseg8_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i16:
+define void @test_vsuxseg2_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i16:
+define void @test_vsuxseg2_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i8:
+define void @test_vsuxseg2_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i8:
+define void @test_vsuxseg2_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i16:
+define void @test_vsuxseg2_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i16:
+define void @test_vsuxseg2_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i32:
+define void @test_vsuxseg2_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i32:
+define void @test_vsuxseg2_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i8:
+define void @test_vsuxseg3_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i8:
+define void @test_vsuxseg3_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i64:
+define void @test_vsuxseg3_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i64:
+define void @test_vsuxseg3_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv64i8:
+define void @test_vsuxseg3_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv64i8:
+define void @test_vsuxseg3_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i16:
+define void @test_vsuxseg3_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i16:
+define void @test_vsuxseg3_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i64:
+define void @test_vsuxseg4_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i64:
+define void @test_vsuxseg4_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i8:
+define void @test_vsuxseg4_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i8:
+define void @test_vsuxseg4_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i8:
+define void @test_vsuxseg4_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i8:
+define void @test_vsuxseg4_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i32:
+define void @test_vsuxseg4_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i32:
+define void @test_vsuxseg4_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv32i8:
+define void @test_vsuxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv32i8:
+define void @test_vsuxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i32:
+define void @test_vsuxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i32:
+define void @test_vsuxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i16:
+define void @test_vsuxseg2_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i16:
+define void @test_vsuxseg2_mask_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i64:
+define void @test_vsuxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i64:
+define void @test_vsuxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i16:
+define void @test_vsuxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i16:
+define void @test_vsuxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv32i16:
+define void @test_vsuxseg2_nxv4f64_nxv4i64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv32i16:
+define void @test_vsuxseg2_mask_nxv4f64_nxv4i64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i32:
+define void @test_vsuxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i32:
+define void @test_vsuxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i8:
+define void @test_vsuxseg2_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i8:
+define void @test_vsuxseg2_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i64:
+define void @test_vsuxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i64:
+define void @test_vsuxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i32:
+define void @test_vsuxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i32:
+define void @test_vsuxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i16:
+define void @test_vsuxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i16:
+define void @test_vsuxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i8:
+define void @test_vsuxseg3_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i8:
+define void @test_vsuxseg3_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i16:
+define void @test_vsuxseg3_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i16:
+define void @test_vsuxseg3_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i32:
+define void @test_vsuxseg3_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i32:
+define void @test_vsuxseg3_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i8:
+define void @test_vsuxseg3_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i8:
+define void @test_vsuxseg3_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i64:
+define void @test_vsuxseg4_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i64:
+define void @test_vsuxseg4_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv64i8:
+define void @test_vsuxseg4_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv64i8:
+define void @test_vsuxseg4_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i16:
+define void @test_vsuxseg4_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i16:
+define void @test_vsuxseg4_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i8:
+define void @test_vsuxseg4_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i8:
+define void @test_vsuxseg4_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i8:
+define void @test_vsuxseg5_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i8:
+define void @test_vsuxseg5_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i32:
+define void @test_vsuxseg5_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i32:
+define void @test_vsuxseg5_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i16:
+define void @test_vsuxseg5_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i16:
+define void @test_vsuxseg5_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg4_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i64:
+define void @test_vsuxseg5_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i64:
+define void @test_vsuxseg5_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i16:
+define void @test_vsuxseg6_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i16:
+define void @test_vsuxseg6_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv32i16:
+define void @test_vsuxseg6_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv32i16:
+define void @test_vsuxseg6_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i32:
+define void @test_vsuxseg6_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i32:
+define void @test_vsuxseg6_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i8:
+define void @test_vsuxseg6_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i8:
+define void @test_vsuxseg6_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i64:
+define void @test_vsuxseg7_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i64:
+define void @test_vsuxseg7_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i32:
+define void @test_vsuxseg7_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i32:
+define void @test_vsuxseg7_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i16:
+define void @test_vsuxseg7_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i16:
+define void @test_vsuxseg7_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i8:
+define void @test_vsuxseg7_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i8:
+define void @test_vsuxseg7_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i16:
+define void @test_vsuxseg8_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i16:
+define void @test_vsuxseg8_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i32:
+define void @test_vsuxseg8_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i32:
+define void @test_vsuxseg8_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i8:
+define void @test_vsuxseg8_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i8:
+define void @test_vsuxseg8_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i64:
+define void @test_vsuxseg8_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i64:
+define void @test_vsuxseg8_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv64i8:
+define void @test_vsuxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv64i8:
+define void @test_vsuxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i16:
+define void @test_vsuxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i16:
+define void @test_vsuxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+define void @test_vsuxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i64:
+define void @test_vsuxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i8:
+define void @test_vsuxseg2_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i8:
+define void @test_vsuxseg2_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i8:
+define void @test_vsuxseg3_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i8:
+define void @test_vsuxseg3_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i32:
+define void @test_vsuxseg3_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i32:
+define void @test_vsuxseg3_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv32i8:
+define void @test_vsuxseg3_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv32i8:
+define void @test_vsuxseg3_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i32:
+define void @test_vsuxseg3_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i32:
+define void @test_vsuxseg3_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i16:
+define void @test_vsuxseg4_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i16:
+define void @test_vsuxseg4_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg5_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i64:
+define void @test_vsuxseg4_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i64:
+define void @test_vsuxseg4_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i16:
+define void @test_vsuxseg4_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i16:
+define void @test_vsuxseg4_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv32i16:
+define void @test_vsuxseg4_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv32i16:
+define void @test_vsuxseg4_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i32:
+define void @test_vsuxseg5_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i32:
+define void @test_vsuxseg5_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i8:
+define void @test_vsuxseg5_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i8:
+define void @test_vsuxseg5_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i64:
+define void @test_vsuxseg5_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i64:
+define void @test_vsuxseg5_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i32:
+define void @test_vsuxseg5_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i32:
+define void @test_vsuxseg5_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i16:
+define void @test_vsuxseg6_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13304,16 +13407,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i16:
+define void @test_vsuxseg6_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13321,19 +13424,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i8:
+define void @test_vsuxseg6_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13341,16 +13444,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i8:
+define void @test_vsuxseg6_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13358,19 +13461,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i16:
+define void @test_vsuxseg6_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13378,16 +13481,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i16:
+define void @test_vsuxseg6_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13395,19 +13498,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i32:
+define void @test_vsuxseg6_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13415,16 +13518,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i32:
+define void @test_vsuxseg6_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13432,19 +13535,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i8:
+define void @test_vsuxseg7_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13452,16 +13555,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i8:
+define void @test_vsuxseg7_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13469,19 +13573,20 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i64:
+define void @test_vsuxseg7_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13489,16 +13594,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i64:
+define void @test_vsuxseg7_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13506,56 +13612,59 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv64i8:
+define void @test_vsuxseg7_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv64i8:
+define void @test_vsuxseg7_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i16:
+define void @test_vsuxseg7_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13563,16 +13672,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i16:
+define void @test_vsuxseg7_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13580,56 +13690,61 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i64:
+define void @test_vsuxseg8_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i64:
+define void @test_vsuxseg8_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i8:
+define void @test_vsuxseg8_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13637,16 +13752,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i8:
+define void @test_vsuxseg8_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13654,19 +13771,21 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i8:
+define void @test_vsuxseg8_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13674,16 +13793,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i8:
+define void @test_vsuxseg8_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13691,19 +13812,21 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i32:
+define void @test_vsuxseg8_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -13711,16 +13834,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i32:
+define void @test_vsuxseg8_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -13728,674 +13853,541 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv32i8:
+define void @test_vsuxseg2_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv32i8:
+define void @test_vsuxseg2_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i32:
+define void @test_vsuxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i32:
+define void @test_vsuxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i16:
+define void @test_vsuxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i16:
+define void @test_vsuxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg6_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i64:
+define void @test_vsuxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i64:
+define void @test_vsuxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv16i16:
+define void @test_vsuxseg3_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv16i16:
+define void @test_vsuxseg3_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv32i16:
+define void @test_vsuxseg3_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv32i16:
+define void @test_vsuxseg3_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i32:
+define void @test_vsuxseg3_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i32:
+define void @test_vsuxseg3_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv16i8:
+define void @test_vsuxseg3_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv16i8:
+define void @test_vsuxseg3_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i64:
+define void @test_vsuxseg4_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i64:
+define void @test_vsuxseg4_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i32:
+define void @test_vsuxseg4_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i32:
+define void @test_vsuxseg4_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i16:
+define void @test_vsuxseg4_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i16:
+define void @test_vsuxseg4_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i8:
+define void @test_vsuxseg4_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i8:
+define void @test_vsuxseg4_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i16:
+define void @test_vsuxseg5_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i16:
+define void @test_vsuxseg5_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i32:
+define void @test_vsuxseg5_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i32:
+define void @test_vsuxseg5_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i8:
+define void @test_vsuxseg5_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i8:
+define void @test_vsuxseg5_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i64:
+define void @test_vsuxseg5_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i64:
+define void @test_vsuxseg5_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i16:
+define void @test_vsuxseg6_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14403,17 +14395,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i16:
+define void @test_vsuxseg6_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14421,59 +14412,56 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i64:
+define void @test_vsuxseg6_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i64:
+define void @test_vsuxseg6_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i8:
+define void @test_vsuxseg6_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14481,17 +14469,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i8:
+define void @test_vsuxseg6_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14499,20 +14486,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i8:
+define void @test_vsuxseg6_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14520,17 +14506,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i8:
+define void @test_vsuxseg6_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14538,20 +14523,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i32:
+define void @test_vsuxseg7_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14560,16 +14544,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i32:
+define void @test_vsuxseg7_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14578,19 +14562,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv32i8:
+define void @test_vsuxseg7_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14599,16 +14583,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv32i8:
+define void @test_vsuxseg7_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14617,58 +14601,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i16:
+define void @test_vsuxseg7_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14677,16 +14622,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i16:
+define void @test_vsuxseg7_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14695,19 +14640,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg7_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i64:
+define void @test_vsuxseg7_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14716,16 +14661,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i64:
+define void @test_vsuxseg7_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14734,19 +14679,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv16i16:
+define void @test_vsuxseg8_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14756,16 +14701,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv16i16:
+define void @test_vsuxseg8_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14775,60 +14720,19 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i32:
+define void @test_vsuxseg8_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14838,16 +14742,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i32:
+define void @test_vsuxseg8_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14857,19 +14761,19 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv16i8:
+define void @test_vsuxseg8_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14879,16 +14783,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv16i8:
+define void @test_vsuxseg8_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14898,19 +14802,19 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i64:
+define void @test_vsuxseg8_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -14920,16 +14824,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i64:
+define void @test_vsuxseg8_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -14939,675 +14843,539 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i32:
+define void @test_vsuxseg2_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i32:
+define void @test_vsuxseg2_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i16:
+define void @test_vsuxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i16:
+define void @test_vsuxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i8:
+define void @test_vsuxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i8:
+define void @test_vsuxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i16:
+define void @test_vsuxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i16:
+define void @test_vsuxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i32:
+define void @test_vsuxseg3_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i32:
+define void @test_vsuxseg3_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i8:
+define void @test_vsuxseg3_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i8:
+define void @test_vsuxseg3_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i64:
+define void @test_vsuxseg3_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i64:
+define void @test_vsuxseg3_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv64i8:
+define void @test_vsuxseg3_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv64i8:
+define void @test_vsuxseg3_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i16:
+define void @test_vsuxseg4_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i16:
+define void @test_vsuxseg4_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i64:
+define void @test_vsuxseg4_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i64:
+define void @test_vsuxseg4_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i8:
+define void @test_vsuxseg4_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i8:
+define void @test_vsuxseg4_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i8:
+define void @test_vsuxseg4_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i8:
+define void @test_vsuxseg4_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i32:
+define void @test_vsuxseg5_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i32:
+define void @test_vsuxseg5_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv32i8:
+define void @test_vsuxseg5_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv32i8:
+define void @test_vsuxseg5_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv16i32:
+define void @test_vsuxseg5_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv16i32:
+define void @test_vsuxseg5_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i16:
+define void @test_vsuxseg5_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i16:
+define void @test_vsuxseg5_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg8_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i64:
+define void @test_vsuxseg6_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -15615,18 +15383,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i64:
+define void @test_vsuxseg6_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -15634,447 +15400,512 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv16i16:
+define void @test_vsuxseg6_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv16i16:
+define void @test_vsuxseg6_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv32i16:
+define void @test_vsuxseg6_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv32i16:
+define void @test_vsuxseg6_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i32:
+define void @test_vsuxseg6_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i32:
+define void @test_vsuxseg6_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv16i8:
+define void @test_vsuxseg7_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv16i8:
+define void @test_vsuxseg7_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i64:
+define void @test_vsuxseg7_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i64:
+define void @test_vsuxseg7_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i32:
+define void @test_vsuxseg7_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i32:
+define void @test_vsuxseg7_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i16:
+define void @test_vsuxseg7_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i16:
+define void @test_vsuxseg7_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i16:
+define void @test_vsuxseg8_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i16:
+define void @test_vsuxseg8_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i32:
+define void @test_vsuxseg8_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i32:
+define void @test_vsuxseg8_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i8:
+define void @test_vsuxseg8_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i8:
+define void @test_vsuxseg8_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i64:
+define void @test_vsuxseg8_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i64:
+define void @test_vsuxseg8_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv64i8:
+define void @test_vsuxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv64i8:
+define void @test_vsuxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i16:
+define void @test_vsuxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
 ; CHECK-NEXT:    vmv1r.v v25, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i16:
+define void @test_vsuxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
 ; CHECK-NEXT:    vmv1r.v v25, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i64:
+define void @test_vsuxseg2_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
@@ -16082,12 +15913,12 @@
 ; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i64:
+define void @test_vsuxseg2_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
@@ -16095,89706 +15926,3142 @@
 ; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i8:
+define void @test_vsuxseg2_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i8:
+define void @test_vsuxseg2_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i32:
+define void @test_vsuxseg3_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i32:
+define void @test_vsuxseg3_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv32i8:
+define void @test_vsuxseg3_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv32i8:
+define void @test_vsuxseg3_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv16i32:
+define void @test_vsuxseg3_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v12, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv16i32:
+define void @test_vsuxseg3_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v12, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i16:
+define void @test_vsuxseg3_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i16:
+define void @test_vsuxseg3_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg2_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i64:
+define void @test_vsuxseg4_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i64:
+define void @test_vsuxseg4_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv16i16:
+define void @test_vsuxseg4_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv16i16:
+define void @test_vsuxseg4_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv32i16:
+define void @test_vsuxseg4_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv32i16:
+define void @test_vsuxseg4_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
 ; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i32:
+define void @test_vsuxseg4_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i32:
+define void @test_vsuxseg4_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv16i8:
+define void @test_vsuxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv16i8:
+define void @test_vsuxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i64:
+define void @test_vsuxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i64:
+define void @test_vsuxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i32:
+define void @test_vsuxseg2_nxv8f32_nxv8i64(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i32:
+define void @test_vsuxseg2_mask_nxv8f32_nxv8i64(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i8:
+define void @test_vsuxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i8:
+define void @test_vsuxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i64:
+define void @test_vsuxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i64:
+define void @test_vsuxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv64i8:
+define void @test_vsuxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv64i8:
+define void @test_vsuxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i16:
+define void @test_vsuxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i16:
+define void @test_vsuxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i64:
+define void @test_vsuxseg2_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i64:
+define void @test_vsuxseg2_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i8:
+define void @test_vsuxseg3_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i8:
+define void @test_vsuxseg3_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i8:
+define void @test_vsuxseg3_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i8:
+define void @test_vsuxseg3_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i32:
+define void @test_vsuxseg3_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i32:
+define void @test_vsuxseg3_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv32i8:
+define void @test_vsuxseg3_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv32i8:
+define void @test_vsuxseg3_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i16:
+define void @test_vsuxseg4_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i16:
+define void @test_vsuxseg4_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i64:
+define void @test_vsuxseg4_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i64:
+define void @test_vsuxseg4_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv16i16:
+define void @test_vsuxseg4_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv16i16:
+define void @test_vsuxseg4_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i32:
+define void @test_vsuxseg4_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i32:
+define void @test_vsuxseg4_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv16i8:
+define void @test_vsuxseg2_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv16i8:
+define void @test_vsuxseg2_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i64:
+define void @test_vsuxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i64:
+define void @test_vsuxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i32:
+define void @test_vsuxseg2_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv16i8:
+define void @test_vsuxseg2_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv16i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv16i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv16i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv16i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv16i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv16i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv32i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv32i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv32i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv32i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv32i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv32i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv16i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv16i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv16i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv16i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv16i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv16i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv1i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv1i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv1i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv1i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv1i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv1i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv1i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv1i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv1i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv1i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv1i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv1i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv8i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv8i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv8i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv8i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv8i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv8i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv1i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv1i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv1i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv1i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv1i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv1i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv2i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv2i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv2i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv2i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv2i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv2i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv8i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv8i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv8i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv8i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv8i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv8i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv64i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv64i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv64i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv64i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv64i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv64i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv8i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv8i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv8i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv8i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv8i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv8i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv1i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv1i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv1i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv1i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv1i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv1i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv2i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv2i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv2i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv2i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv2i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv2i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv8i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv8i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv8i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv8i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv8i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv8i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv32i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv32i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv32i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv32i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv32i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv32i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv16i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv16i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv16i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv16i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv16i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv16i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv2i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv2i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv2i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv2i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv2i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv2i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i64.nxv2i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv2i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i64_nxv2i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv2i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i64_nxv2i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv2i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv16i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv16i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv32i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv32i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv16i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv16i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv64i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv64i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv64i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv64i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv8i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv8i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv32i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv32i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv16i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv16i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i16>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv16i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv16i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i32>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i8>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv16i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv16i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i64>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i32>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i16>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i8>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i16>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i32>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i8>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i64>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv64i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 64 x i8>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv64i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv64i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv64i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i16>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i64>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i8>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i8>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i32>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i32>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv16i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv16i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i16>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i64>, <vscale x 32 x i1>, i64)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv32i16(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv32i16(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i32(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i32(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i64(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i64(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i32(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i32(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i16(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i16(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i8(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i8(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i16(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i16(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i32(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i32(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i8(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i8(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i64(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i64(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv64i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv64i8(<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv64i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv64i8(<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i16(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i16(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i64(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i64(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i8(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i8(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i8(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i8(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i32(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i32(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv32i8(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv32i8(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i16(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i16(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i64(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i64(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv16i16(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv16i16(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv32i16(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv32i16(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv16i8(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv16i8(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i64(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i64(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i32(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i32(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i16(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i16(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i16(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i16(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i32(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i32(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i8(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i8(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv4i64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv4i64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv64i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv64i8(<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv64i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv64i8(<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i64(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i64(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i8(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i8(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i8(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i8(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i32(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i32(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv32i8(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv32i8(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv16i32(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv16i32(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i16(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i16(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i64(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i64(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv16i16(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv16i16(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv32i16(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv32i16(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i32(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i32(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv16i8(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv16i8(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i64(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i64(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i32(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i32(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i8(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i8(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i16(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i16(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i32(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i32(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i64(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i64(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv64i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv64i8(<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv64i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv64i8(<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i16(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i16(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv8i64(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv8i64(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i8(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i8(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i8(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i8(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv32i8(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv32i8(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv16i32(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv16i32(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i16(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i16(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i64(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i64(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg6_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg7_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg8_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg2_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg3_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg4_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg5_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg6_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg7_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
-
-define void @test_vsuxseg8_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv16i16:
+define void @test_vsuxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv16i16:
+define void @test_vsuxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv32i16:
+define void @test_vsuxseg3_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv32i16:
+define void @test_vsuxseg3_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i32:
+define void @test_vsuxseg3_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i32:
+define void @test_vsuxseg3_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv16i8:
+define void @test_vsuxseg3_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv16i8:
+define void @test_vsuxseg3_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i64:
+define void @test_vsuxseg3_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i64:
+define void @test_vsuxseg3_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i32:
+define void @test_vsuxseg4_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i32:
+define void @test_vsuxseg4_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i16:
+define void @test_vsuxseg4_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i16:
+define void @test_vsuxseg4_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i8:
+define void @test_vsuxseg4_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i8:
+define void @test_vsuxseg4_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i16:
+define void @test_vsuxseg4_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i16:
+define void @test_vsuxseg4_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i32:
+define void @test_vsuxseg5_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i32:
+define void @test_vsuxseg5_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i8:
+define void @test_vsuxseg5_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i8:
+define void @test_vsuxseg5_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i64:
+define void @test_vsuxseg5_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i64:
+define void @test_vsuxseg5_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv64i8:
+define void @test_vsuxseg5_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv64i8:
+define void @test_vsuxseg5_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i16:
+define void @test_vsuxseg6_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i16:
+define void @test_vsuxseg6_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i64:
+define void @test_vsuxseg6_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i64:
+define void @test_vsuxseg6_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i8:
+define void @test_vsuxseg6_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i8:
+define void @test_vsuxseg6_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i8:
+define void @test_vsuxseg6_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i8:
+define void @test_vsuxseg6_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i32:
+define void @test_vsuxseg7_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i32:
+define void @test_vsuxseg7_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv32i8:
+define void @test_vsuxseg7_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv32i8:
+define void @test_vsuxseg7_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv16i32:
+define void @test_vsuxseg7_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv16i32:
+define void @test_vsuxseg7_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i16:
+define void @test_vsuxseg7_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i16:
+define void @test_vsuxseg7_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg2_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i64:
+define void @test_vsuxseg8_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i64:
+define void @test_vsuxseg8_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv16i16:
+define void @test_vsuxseg8_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv16i16:
+define void @test_vsuxseg8_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv32i16:
+define void @test_vsuxseg8_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv32i16:
+define void @test_vsuxseg8_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i32:
+define void @test_vsuxseg8_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i32:
+define void @test_vsuxseg8_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv16i8:
+define void @test_vsuxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv16i8:
+define void @test_vsuxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i64:
+define void @test_vsuxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i64:
+define void @test_vsuxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i32:
+define void @test_vsuxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i32:
+define void @test_vsuxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i16:
+define void @test_vsuxseg2_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i16:
+define void @test_vsuxseg2_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i8:
+define void @test_vsuxseg3_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i8:
+define void @test_vsuxseg3_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i16:
+define void @test_vsuxseg3_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i16:
+define void @test_vsuxseg3_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+define void @test_vsuxseg3_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i32:
+define void @test_vsuxseg3_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i8:
+define void @test_vsuxseg3_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i8:
+define void @test_vsuxseg3_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i64:
+define void @test_vsuxseg4_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i64:
+define void @test_vsuxseg4_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv64i8:
+define void @test_vsuxseg4_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv64i8:
+define void @test_vsuxseg4_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i16:
+define void @test_vsuxseg4_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i16:
+define void @test_vsuxseg4_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i64:
+define void @test_vsuxseg4_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i64:
+define void @test_vsuxseg4_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i8:
+define void @test_vsuxseg5_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i8:
+define void @test_vsuxseg5_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i8:
+define void @test_vsuxseg5_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i8:
+define void @test_vsuxseg5_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i32:
+define void @test_vsuxseg5_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i32:
+define void @test_vsuxseg5_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv32i8:
+define void @test_vsuxseg5_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv32i8:
+define void @test_vsuxseg5_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv16i32:
+define void @test_vsuxseg6_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv16i32:
+define void @test_vsuxseg6_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i16:
+define void @test_vsuxseg6_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i16:
+define void @test_vsuxseg6_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg3_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i64:
+define void @test_vsuxseg6_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i64:
+define void @test_vsuxseg6_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv16i16:
+define void @test_vsuxseg6_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv16i16:
+define void @test_vsuxseg6_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv32i16:
+define void @test_vsuxseg7_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv32i16:
+define void @test_vsuxseg7_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i32:
+define void @test_vsuxseg7_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i32:
+define void @test_vsuxseg7_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv16i8:
+define void @test_vsuxseg7_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv16i8:
+define void @test_vsuxseg7_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i64:
+define void @test_vsuxseg7_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i64:
+define void @test_vsuxseg7_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i32:
+define void @test_vsuxseg8_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i32:
+define void @test_vsuxseg8_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i16:
+define void @test_vsuxseg8_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i16:
+define void @test_vsuxseg8_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i8:
+define void @test_vsuxseg8_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i8:
+define void @test_vsuxseg8_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i16:
+define void @test_vsuxseg8_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i16:
+define void @test_vsuxseg8_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei64.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i32:
+define void @test_vsuxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i32:
+define void @test_vsuxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i8:
+define void @test_vsuxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i8:
+define void @test_vsuxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i64:
+define void @test_vsuxseg2_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i64:
+define void @test_vsuxseg2_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg2ei64.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv64i8:
+define void @test_vsuxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv64i8:
+define void @test_vsuxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i16:
+define void @test_vsuxseg3_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i16:
+define void @test_vsuxseg3_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i64:
+define void @test_vsuxseg3_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i64:
+define void @test_vsuxseg3_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i8:
+define void @test_vsuxseg3_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg3ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i8:
+define void @test_vsuxseg3_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg3ei64.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i8:
+define void @test_vsuxseg3_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i8:
+define void @test_vsuxseg3_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i32:
+define void @test_vsuxseg4_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i32:
+define void @test_vsuxseg4_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv32i8:
+define void @test_vsuxseg4_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv32i8:
+define void @test_vsuxseg4_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
-
-define void @test_vsuxseg4_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i16:
+define void @test_vsuxseg4_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i16:
+define void @test_vsuxseg4_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, i64)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
 
-define void @test_vsuxseg4_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i64:
+define void @test_vsuxseg4_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i64:
+define void @test_vsuxseg4_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei64.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
   ret void
 }